Abstract: The stress-reduced layer system has at least one first layer of polycrystalline or single-crystal semiconductor material, which adjoins a microcrystalline or amorphous, conducting or insulating second layer. The semiconductor layer is doped with at least two dopants of the same conductivity type, of which at least one is suitable for reducing mechanical stresses at the interface. The stress-reduced layer system, in a further embodiment, has at least one first layer of semiconductor material, conducting or insulating material and at least one conducting or insulating second layer. A further semiconductor layer, which is doped with at least one dopant that is suitable for reducing mechanical stresses at the interface between the second layer and the first layer, is arranged between the first layer and the second layer or it is applied to the surface of the first layer or the second layer that is opposite from the interface.

Abstract: Several a transistor, which are inhibited short channel effect moderately according to each transistor's channel length, are formed on a same SOI substrate. In the present invention, forming a first transistor on SOI substrate, and forming a second transistor which has a gate electrode whose length is longer than a gate length of the first transistor in a channel direction The impurities are doped from above a surface of the SOI substrate in an oblique direction against the surface, and from source side and drain side of the first transistor and the second transistor. By this means, a pocket layer is formed under an insulator layer of a SOI substrate.

Abstract: There is provided a field effect transistor which is suitable for a power amplifier application or the like, and have a double recess structure with superior repeatability. A film thickness of an AlGaAs layer can determine a depth of a second step of a recess uniquely by using the AlGaAs layer and an InGaP layer with a higher etching selection ratio, a double recess structure can be formed with desirable repeatability, and a high withstand voltage device suitable for a power amplifier application or the like is achieved by making both side surfaces of a gate electrode into the AlGaAs layer.

Abstract: The present invention is a method for forming super steep doping profiles in MOS transistor structures. The method comprises forming a carbon containing layer (110) beneath the gate dielectric (50) and source and drain regions (80) of a MOS transistor. The carbon containing layer (110) will prevent the diffusion of dopants into the region (40) directly beneath the gate dielectric layer (50).

Abstract: A light emitting diode with high heat dissipation includes a substrate, a LED chip, a metal light reflection layer, a first lens, a holder, and a second lens. The substrate has an upper surface formed with a positive electrode and an opposite electrode, and a lower surface opposite to the upper surface. The LED chip is arranged on the upper surface of the substrate, and is electrically connected to the positive electrode and the opposite electrode by wires. The metal light reflection layer is located on the upper surface of the substrate for surrounding the LED chip, and reflecting the light emitted from the LED chip. The first lens is mounted on the metal light reflection layer for encapsulating the LED chip. The holder is mounted on the substrate to cover the first lens. And the second lens arranged on the holder.

Abstract: A method and structure are provided with reduced gate wrap around to advantageously control for threshold voltage and increase stability in semiconductor devices. A spacer is provided aligned to field dielectric layers to protect the dielectric layers during subsequent etch processes. The spacer is then removed prior to subsequently forming a part of a gate oxide layer and a gate conductor layer. Advantageously, the spacer protects the corner area o the field dielectric and also allows for enhanced thickness of the gate oxide near the corners.

Abstract: A decoupling capacitor is provided for a semiconductor device and may include a first low dielectric insulator layer and a low resistance conductor formed into at least two interdigitized patterns on the surface of the first low dielectric insulator in a single interconnect plane. A high dielectric constant material may be provided between the two patterns. A circuit for testing a plurality of these capacitors is also provided which includes a charge monitoring circuit, a coupling circuit and a control circuit.

Abstract: A semiconductor device having reduced self and mutual capacitance of bonded wires is provided by coating the wires with a foamed polymer effectively having a very low dielectric constant. Additional benefits are realized by electrically insulating the wires against short-circuiting, by cushioning the wires with a low modulus sheath, and by protecting chip bond pad metallization TABLE 1 Method of Moments Capacitance Models Wire Dimensions 25 × 25 microns Separation between Wires 63.5 microns Distance to ground ?191 microns Model Dielectric Self capacitance Mutual Capacitance constant of Wire 1 Wire 2 separation Model Dielectric Wire 1 Wire 2- Mutual cap constants self cap self cap pf/cm pf/cm pf/cm Plastic encased 4.0 1.03 0.54 1.57 package Cavity package 4./1.0/4. 0.31 0.12 0.43 Foam sheath 4./1./4./1./4. 0.34 0.16 0.50 wires/molded Wires - no 1.? 0.26 0.13 ?0.39.

Abstract: A gate dielectric (150) for a gate (160) is formed by thermal oxidation simultaneously with as a dielectric on a surface of another gate (140). The dielectric thickness on the other gate is controlled by the dopant concentration in the other gate. The gates may be gates of different MOS transistors, or a select gate and a floating gate of a memory cell. Other features are also provided.

Abstract: A DRAM is provided that can reduce the parasitic capacitance between trench-type stacked cell capacitors in a memory cell region and suppress malfunction caused by noise. The trench-type stacked cell includes a number of capacitors having the same shape. The capacitors are formed in such a manner that storage nodes, a capacitor insulating film, and a plate electrode are buried in each of a plurality of trenches of an interlayer insulating film. The cell layout can be as follows: the capacitors are arranged so that only a part of a side face of one trench is opposite to that of the other; the capacitors are arranged so that the side face of one trench is opposite completely to that of the other and the distance between the opposing side faces is larger at the central portions of the respective trenches; or the cell is arranged so that the plate electrode is buried in a concavity between the cell capacitors.

Abstract: A diode is provided which includes a first-conductivity-type cathode layer, a first-conductivity-type drift layer placed on the cathode region and having a lower concentration than the cathode layer, a generally ring-like second-conductivity-type ring region formed in the drift layer, second-conductivity-type anode region formed in the drift layer located inside the ring region, a cathode electrode formed in contact with the cathode layer, and an anode electrode formed in contact with the anode region, wherein the lowest resistivity of the second-conductivity-type anode region is at least 1/100 of the resistivity of the drift layer, and the thickness of the anode region is smaller than the diffusion depth of the ring region.

Abstract: The semiconductor device comprises: an interlayer insulating film 405 and an insulating film 409, interconnect lines 407, 408a and 408b embedded in the insulating film 409, circuit elements 410a and 410b mounted on the insulating film 409, a packaging film 415 formed so as to cover the circuit elements 410a and 410b, and an electroconductive shielding film 416 formed so as to cover the packaging film 415. The interconnect lines 408a and 408b are configured to be electrically coupled to the shielding film 416.

Abstract: A method of manufacturing a semiconductor device including a die pad section, a first semiconductor chip having a surface on which a first electrode section is formed, a second semiconductor chip having a surface on which a second electrode section is formed, a support member having a surface, lead terminal sections, and a resin encapsulating body, the method including fixing a back surface of the first semiconductor chip and the surface of the support member to the die pad section; fixing a back surface of the second semiconductor chip to the surface of the first semiconductor chip and the surface of the support member; electrically connecting the first and second electrode sections respectively to the lead terminal sections; and sealing the die pad section, the first and second semiconductor chips and the support member with a resin.

Abstract: This is a semiconductor apparatus capable of realizing a sharing of parts without introducing enlargement of the apparatus and deterioration in reliability of the wire bonding in case of responding to various electronic circuits.

Abstract: A semiconductor device has an enhanced di/dt tolerance and a dv/dt tolerance without increasing an ON resistance. An underpad base region is provided on a region in an upper main surface of a semiconductor substrate which is provided under a gate pad, and the underpad base region is not connected to a source electrode and is not coupled to a main base region connected to the source electrode. The underpad base region is brought into a floating state.

Abstract: A SiO2 film serving as a gate dielectric film is formed on a silicon substrate. A seed Si film is formed on the gate dielectric film. A thin SiGe film of a thickness of 50 nm or less is formed on the seed Si film at a temperature between 450° C. and 494° C., and a thin cap Si film of a thickness of 0.5 nm to 5 nm is continuously formed on the thin SiGe film at the same temperature.

Abstract: An IC chip having a protective structure that is distributed over the semiconductor chip in such a manner that it is not possible to trigger a malfunction in the circuit by means of irradiation without the protective structure also being affected by the irradiation. To this end, redundant conductors are provided or connections having radiation-dependent conductivity or dielectric constant are provided or the test lines of a memory are arranged between the bit lines.

Abstract: An apparatus and method for increasing integrated circuit density comprising an upper die and a lower die, the latter preferably a flip chip, which are connected to a conductor-carrying substrate or a leadframe. The upper die is attached back-to-back to the lower die with a layer of adhesive applied over the back side of the lower die. Bond wires or TAB leads are attached between bond pads on the upper die and corresponding conductive trace or lead ends on the substrate. The upper die may be smaller than the lower die such that a small discrete component such as a resistor, capacitor, or the like can be attached to the adhesive not covered by the upper die. Bond wires can be attached between the upper die and the component, as well as between the component and the substrate. One or more additional die may be stacked on the upper die and electrically connected to the substrate. Furthermore, multiple lower dice can be arranged on the substrate to support upper dice bridged between the lower dice.

Abstract: Capacitors for semiconductor devices and methods of fabricating such capacitors are provided. The disclosed capacitor comprises an interlayer dielectric layer (ILD) pattern having an opening exposing a portion of the underlying semiconductor substrate, a silicide pattern formed on the exposed substrate, and a lower electrode covering an inner wall and bottom of the opening. A dielectric layer is formed on the lower electrode, and an upper electrode is disposed on the dielectric layer. The dielectric layer preferably comprises a high k-dielectric layer such as tantalum oxide. The disclosed method comprises forming an ILD pattern with an opening that exposes a portion of a semiconductor substrate forming an optional silicide pattern on the exposed substrate, forming a lower electrode on the inner wall of the opening, and sequentially forming a dielectric layer and an upper electrode on the resulting structure.

Abstract: A method for manufacturing a metal-oxide-semiconductor transistor prevents the occurrence of a contact spiking phenomenon. The method includes forming a metal thin film and an isolation oxidation film on a semiconductor substrate, and selectively etching the isolation oxidation film such that the isolation oxidation film is left remaining only over a field oxidation film; heat treating the semiconductor substrate to form silicide by the metal thin film in gate, source, and drain regions; removing portions of the metal thin film that is not formed into silicide, that is, removing unreacted metal thin film; removing the isolation oxidation film left remaining on the field oxidation film; and heat treating the semiconductor substrate in an oxygen environment to form the unreacted metal thin film remaining on the field oxidation film into a metal oxidation film. The present invention is related also to a semiconductor device that employs a metal-oxide-semiconductor transistor made using the method.