Patents Examined by Hoai V. Pham
  • Patent number: 10854830
    Abstract: A display apparatus includes a display module configured to display an image, and defining a folding area that is in-foldable about an imaginary folding axis, and a plurality of non-folding areas adjacent respective sides of the folding area in a plane, a support member having a plate shape under the display module, an adhesive member between the display module and the support member, and at least one first non-adhesive member overlapping with the folding area and located between the adhesive member and the support member.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: December 1, 2020
    Assignee: Samsung Display Co., Ltd.
    Inventors: Jaiku Shin, Mansik Myeong
  • Patent number: 10854728
    Abstract: According to an exemplary embodiment, a method of forming a vertical device is provided. The method includes: providing a protrusion over a substrate; forming an etch stop layer over the protrusion; laterally etching a sidewall of the etch stop layer; forming an insulating layer over the etch stop layer; forming a film layer over the insulating layer and the etch stop layer; performing chemical mechanical polishing on the film layer and exposing the etch stop layer; etching a portion of the etch stop layer to expose a top surface of the protrusion; forming an oxide layer over the protrusion and the film layer; and performing chemical mechanical polishing on the oxide layer and exposing the film layer.
    Type: Grant
    Filed: December 9, 2019
    Date of Patent: December 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: De-Fang Chen, Teng-Chun Tsai, Cheng-Tung Lin, Li-Ting Wang, Chun-Hung Lee, Ming-Ching Chang, Huan-Just Lin
  • Patent number: 10847716
    Abstract: A phase change memory device includes a bottom electrode, a bottom memory layer, a top memory layer, and a top electrode. The bottom memory layer is over the bottom electrode. The bottom memory layer has a first height and includes a tapered portion and a neck portion. The tapered portion has a second height. A ratio of the second height to the first height is in a range of about 0.2 to about 0.5. The neck portion is between the tapered portion and the bottom electrode. The top memory layer is over the bottom memory layer. The tapered portion of the bottom memory layer tapers in a direction from the top memory layer toward the neck portion. The top electrode is over the top memory layer.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: November 24, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tung-Ying Lee, Shao-Ming Yu, Yu-Chao Lin
  • Patent number: 10847754
    Abstract: A display device includes a light-emitting element layer that emits light with a luminance controlled for each of a plurality of unit pixels constituting an image, and a sealing layer provided on the light-emitting element layer and including a plurality of layers. The plurality of layers of the sealing layer includes at least an inorganic layer provided on the light-emitting element layer, an organic layer provided on the inorganic layer, and an inorganic layer that is an uppermost layer. A density of the inorganic layer that is the uppermost layer in a thickness direction changes in the thickness direction.
    Type: Grant
    Filed: December 3, 2019
    Date of Patent: November 24, 2020
    Assignee: Japan Display Inc.
    Inventors: Akinori Kamiya, Daisuke Kato
  • Patent number: 10847654
    Abstract: Methods and structures for forming strained-channel finFETs are described. Fin structures for finFETs may be formed in two epitaxial layers that are grown over a bulk substrate. A first thin epitaxial layer may be cut and used to impart strain to an adjacent channel region of the finFET via elastic relaxation. The structures exhibit a preferred design range for increasing induced strain and uniformity of the strain over the fin height.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: November 24, 2020
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Nicolas Loubet, Pierre Morin
  • Patent number: 10840464
    Abstract: A highly portable and highly browsable light-emitting device is provided. A light-emitting device that is less likely to be broken is provided. The light-emitting device has a strip-like region having high flexibility and a strip-like region having low flexibility that are arranged alternately. In the region having high flexibility, a light-emitting panel and a plurality of spacers overlap with each other. In the region having low flexibility, the light-emitting panel and a support overlap with each other. When the region having high flexibility is bent, the angle between normals of facing planes of the two adjacent spacers changes according to the bending of the light-emitting panel; thus, a neutral plane can be formed in the light-emitting panel or in the vicinity of the light-emitting panel.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: November 17, 2020
    Assignee: Semiconductor Energy Laboratories Co., Ltd.
    Inventors: Masaaki Hiroki, Akio Endo
  • Patent number: 10825885
    Abstract: A display apparatus includes: a substrate including a display area and a peripheral area adjacent to the display area; a first and a second organic insulating layer each on the substrate; in the display area: a thin film transistor on the substrate; a driving voltage line connected to the thin film transistor and between the first and second organic insulating layers; and a display device connected to the thin film transistor, the first organic insulating layer and the second organic insulating layer being between the display device and the thin film transistor; and in the peripheral area, a common power supply wiring on the substrate and through which a common voltage is supplied to the display device in the display area. The common power supply wiring in the peripheral area and the driving voltage line in the display area are respectively portions of a same first material layer on the substrate.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: November 3, 2020
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Sangho Moon, Chungi You, Sungho Cho
  • Patent number: 10811606
    Abstract: A radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM, the PCM and heating element being situated over a substrate. A contact dielectric is over the PCM. PCM contacts have upper portions and uniform plate slot lower portions. The uniform plate slot lower portions have a total plate resistance RPLATE, and a total plate slot interface resistance RPLATE-INT. The upper portions have a total capacitance CUPPER to the uniform plate slot lower portions, and the PCM has a total capacitance CPCM to the substrate. The uniform plate slot lower portions significantly reduce a product of (RPLATE+RPLATE-INT) and (CUPPER+CPCM). As an alternative to the uniform plate slot lower portions, PCM contacts have segmented lower portions. The segmented lower portions significantly reduce CUPPER.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: October 20, 2020
    Assignee: Newport Fab, LLC
    Inventors: David J. Howard, Jefferson E. Rose, Gregory P. Slovin, Nabil El-Hinnawy, Michael J. DeBar
  • Patent number: 10811605
    Abstract: A radio frequency (RF) switch includes a phase-change material (PCM) and a heating element underlying an active segment of the PCM, the PCM and heating element being situated over a substrate. A contact dielectric is over the PCM. PCM contacts have upper portions and uniform plate slot lower portions. The uniform plate slot lower portions have a total plate resistance RPLATE, and a total plate slot interface resistance RPLATE-INT. The upper portions have a total capacitance CUPPER to the uniform plate slot lower portions, and the PCM has a total capacitance CPCM to the substrate. The uniform plate slot lower portions significantly reduce a product of (RPLATE+RPLATE-INT) and (CUPPER+CPCM). As an alternative to the uniform plate slot lower portions, PCM contacts have segmented lower portions. The segmented lower portions significantly reduce CUPPER.
    Type: Grant
    Filed: December 31, 2019
    Date of Patent: October 20, 2020
    Assignee: Newport Fab, LLC dba Jazz Semiconductor
    Inventors: David J. Howard, Jefferson E. Rose, Gregory P. Slovin, Nabil El-Hinnawy, Michael J. DeBar
  • Patent number: 10804172
    Abstract: A semiconductor package device includes a substrate, an electronic component, a ring frame, an encapsulant, a thermal conducting material and a lid. The electronic component is disposed on the substrate. The ring frame is disposed on the substrate and surrounds the electronic component. The encapsulant encapsulates the electronic component and a first portion of the ring frame. The encapsulant exposes a second portion of the ring frame. The encapsulant and the second portion of the ring frame define a space. The thermal conducting material is disposed in the space. The lid is disposed on the thermal conducting material and connects with the second portion of the ring frame.
    Type: Grant
    Filed: December 10, 2018
    Date of Patent: October 13, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Hsu-Nan Fang
  • Patent number: 10797203
    Abstract: A light emitting device includes a light-transmissive member including a first surface, a second surface opposite to the first surface, and third surfaces connected to the first surface and the second surface. A phosphor layer faces the second surface of the light-transmissive member. A reflective member faces side surfaces of the phosphor layer and the third surfaces of the light-transmissive member. The light-emitting element has a top surface facing the phosphor layer, a bottom surface opposite to the top surface, and side surfaces connecting the top surface and the bottom surface. The phosphor layer has a bonding surface facing the light emitting element. A first dielectric multilayer film is arranged on at least one of side surfaces of the light-emitting element without being provided on the bonding surface of the phosphor layer.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: October 6, 2020
    Assignee: NICHIA CORPORATION
    Inventors: Daisuke Iwakura, Yoshiki Inoue
  • Patent number: 10790413
    Abstract: One embodiment comprises: a substrate; a first conductive semiconductor layer disposed on the substrate; a second conductive semiconductor layer disposed on the first conductive semiconductor layer; and an active layer disposed between the first conductive semiconductor layer and the second conductive semiconductor layer, wherein the first conductive semiconductor layer comprises a first area where a partial area of the first conductive semiconductor layer is exposed, and comprises an inclination part which is disposed between the upper surface of the first area and the upper surface of the second conductive semiconductor layer, wherein the inclination part comprises a first edge making contact with the upper surface of the second conductive semiconductor layer, and a second edge making contact with the upper surface of the first area of the first conductive semiconductor layer, wherein the ratio of a first length to a second length is 1:0.87 to 1:4.
    Type: Grant
    Filed: December 28, 2016
    Date of Patent: September 29, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Youn Joon Sung, Yong Gyeong Lee, Kwang Yong Choi
  • Patent number: 10784378
    Abstract: Ultra-scaled fin pitch processes having dual gate dielectrics are described. For example, a semiconductor structure includes first and second semiconductor fins above a substrate. A first gate structure includes a first gate electrode over a top surface and laterally adjacent to sidewalls of the first semiconductor fin, a first gate dielectric layer between the first gate electrode and the first semiconductor fin and along sidewalls of the first gate structure, and a second gate dielectric layer between the first gate electrode and the first gate dielectric layer and along the first gate dielectric layer along the sidewalls of the first gate electrode. A second gate structure includes a second gate electrode over a top surface and laterally adjacent to sidewalls of the second semiconductor fin, and the second gate dielectric layer between the second gate electrode and the second semiconductor fin and along sidewalls of the second gate electrode.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 22, 2020
    Assignee: Intel Corporation
    Inventors: Walid M. Hafez, Roman W. Olac-Vaw, Joodong Park, Chen-Guan Lee, Chia-Hong Jan, Everett S. Cassidy-Comfort
  • Patent number: 10784033
    Abstract: Embodiments of the invention include a microelectronic device and methods of forming a microelectronic device. In an embodiment the microelectronic device includes a semiconductor die and an inductor that is electrically coupled to the semiconductor die. The inductor may include one or more conductive coils that extend away from a surface of the semiconductor die. In an embodiment each conductive coils may include a plurality of traces. For example, a first trace and a third trace may be formed over a first dielectric layer and a second trace may be formed over a second dielectric layer and over a core. A first via through the second dielectric layer may couple the first trace to the second trace, and a second via through the second dielectric layer may couple the second trace to the third trace.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: September 22, 2020
    Assignee: Intel IP Corporation
    Inventors: Andreas Wolter, Thorsten Meyer, Gerhard Knoblinger
  • Patent number: 10777478
    Abstract: A semiconductor package device includes a first die having a first surface and a second surface opposite to the first surface, and a first adhesive layer disposed on the first surface of the first die. The semiconductor package device further includes an encapsulant layer encapsulating the first die and the first adhesive layer, and a first conductive via disposed in the first adhesive layer and electrically connected to the first die.
    Type: Grant
    Filed: July 13, 2017
    Date of Patent: September 15, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Bernd Karl Appelt, Kay Stefan Essig
  • Patent number: 10777491
    Abstract: A package comprising a carrier, at least one electronic chip mounted on one side of the carrier, an encapsulant at least partially encapsulating the at least one electronic chip and partially encapsulating the carrier, and at least one component attached to an opposing other side of the carrier via at least one contact opening.
    Type: Grant
    Filed: February 20, 2019
    Date of Patent: September 15, 2020
    Assignee: Infineon Technologies AG
    Inventors: Thorsten Scharf, Thorsten Meyer
  • Patent number: 10777671
    Abstract: Embodiments of the invention include a semiconductor device and methods of forming such devices. In an embodiment, the semiconductor device includes a source region, a drain region, and a channel region formed between the source region and drain region. In an embodiment, a first interlayer dielectric (ILD) may be formed over the channel region, and a first opening is formed through the first ILD. In an embodiment, a second ILD may be formed over the first ILD, and a second opening is formed through the second ILD. Embodiments of the invention include the second opening being offset from the first opening. Embodiments may also include a gate electrode formed through the first opening and the second opening. In an embodiment, the offset between the first opening and the second opening results in the formation of a field plate and a spacer that reduces a gate length of the semiconductor device.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: September 15, 2020
    Assignee: Intel Corporation
    Inventors: Han Wui Then, Sansaptak Dasgupta, Marko Radosavljevic
  • Patent number: 10777601
    Abstract: An image sensor array of shared pixel units fabricated by a CMOS technology, wherein each pixel unit includes a plurality of photodiodes and respective transfer transistors and floating drains whose layout constitutes mirror images. The plurality of photodiodes each share a single reset transistor and source follower amplifier transistor wherein the shared floating diode is spaced at the minimum distance from a gate electrode of the source follower transistor as is allowed by the CMOS fabrication technology chosen to manufacture the image sensor array.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: September 15, 2020
    Assignee: SmartSens Technology (HK) Co., Ltd
    Inventors: Chen Xu, Zexu Shao, Xin Wang
  • Patent number: 10763185
    Abstract: Packaged semiconductor components having substantially rigid support member are disclosed. The packages can include a semiconductor die and a support member proximate to the semiconductor die. The support member is at least substantially rigid. The packages can further include an adhesive between the support member and the semiconductor die and adhesively attaching the support member to the semiconductor die. The packages can also include a substrate carrying the semiconductor die and the support member attached to the semiconductor die.
    Type: Grant
    Filed: April 23, 2019
    Date of Patent: September 1, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Matt E. Schwab, J. Michael Brooks, David J. Corisis
  • Patent number: 10756210
    Abstract: A transistor device including a transistor including a body disposed on a substrate, a gate stack contacting at least two adjacent sides of the body and a source and a drain on opposing sides of the gate stack and a channel defined in the body between the source and the drain, wherein a conductivity of the channel is similar to a conductivity of the source and the drain. An input/output (IO) circuit including a driver circuit coupled to the logic circuit, the driver circuit including at least one transistor device is described. A method including forming a channel of a transistor device on a substrate including an electrical conductivity; forming a source and a drain on opposite sides of the channel, wherein the source and the drain include the same electrical conductivity as the channel; and forming a gate stack on the channel.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: August 25, 2020
    Assignee: Intel Corporation
    Inventors: Chia-Hong Jan, Walid M. Hafez, Hsu-Yu Chang, Neville L. Dias, Rahul Ramaswamy, Roman W. Olac-Vaw, Chen-Guan Lee