Abstract: A method includes forming an inter-layer insulation layer on a substrate, forming a plug material penetrating the inter-layer insulation layer and contacting a portion of the substrate, forming a contact plug by etching the plug material, forming a trench exposing a side wall of the contact plug by etching the substrate and the inter-layer insulation layer to be aligned with a side wall of the contact plug, forming a gate insulation layer on a surface of the trench and the exposed side wall of the contact plug, and forming a gate electrode partially filling the trench on the gate insulation layer.

Abstract: A semiconductor device includes a substrate having an array region defined thereon, a ring of magnetic tunneling junction (MTJ) region surrounding the array region, a gap between the array region and the ring of MTJ region, and metal interconnect patterns overlapping part of the ring of MTJ region. Preferably, the array region includes a magnetic random access memory (MRAM) region and a logic region and the ring of MTJ region further includes a first MTJ region and a second MTJ region extending along a first direction and a third MTJ region and a fourth MTJ region extending along a second direction.

Abstract: The disclosure relates to a buried bit line and a forming method thereof, the buried bit line is formed in a bit line slot of a substrate, the buried bit line includes a first bit line layer formed in the bit line slot, a first blocking layer and a second bit line layer. A top of the first bit line layer is lower than a surface of the substrate. The first blocking layer is at least partially formed between the first bit line layer and an inner wall of the bit line slot. The second bit line layer is formed in the bit line slot and configured to communicate the first bit line layer with a drain region in the substrate.

Abstract: A semiconductor memory device includes a substrate including an element separation film and an active region defined by the element separation film, a bit line structure on the substrate, a trench in the element separation film and the active region, the trench on at least one side of the bit line structure and including a first portion in the element separation film and a second portion in the active region, a bottom face of the first portion placed above a bottom face of the second portion, a single crystal storage contact filling the trench, and an information storage element electrically connected to the single crystal storage contact.

Abstract: A contact forming method may include providing a semiconductor substrate including a silicon oxide film to an interior of a chamber, subjecting a surface of the silicon oxide film to plasma nitrification treatment, supplying a source gas including TiCl4 and H2 onto the silicon oxide film subjected to the plasma nitrification treatment, and forming a barrier layer by igniting a plasma using the source gas.

Abstract: A display device may include a substrate including a display area and a non-display area; and pixels provided in the display area, each of the plurality of pixels comprising sub-pixels. Each of the plurality of sub-pixels may include a pixel circuit layer including at least one transistor, and a display element layer including an emission area and a peripheral area, a first electrode provided in the emission area, a second electrode spaced apart from the first electrode, at least one light emitting element provided in the emission area, and including a first end electrically connected to the first electrode, and a second end electrically connected to the second electrode; a first connection line provided in the peripheral area; and a bridge pattern provided in the peripheral area, and diverging from the first connection line. The bridge pattern may be electrically disconnected from each of the first and second electrodes.

Abstract: The present disclosure provides one embodiment of a method making semiconductor structure. The method includes forming a composite stress layer on a semiconductor substrate, wherein the forming of the composite stress layer includes forming a first stress layer of a dielectric material with a first compressive stress and forming a second stress layer of the dielectric material with a second compressive stress on the first stress layer, the second compressive stress being greater than the first compressive stress; and patterning the semiconductor substrate to form fin active regions using the composite stress layer as an etch mask.

Abstract: An organic light-emitting component is disclosed. The component includes an organic functional layer stack between two electrodes, where the organic functional layer stack has at least two organic light-emitting layers and at least one charge generation layer, and where at least one of the at least two organic light-emitting layers is part of the charge generation layer.

Abstract: The present disclosure relates to a system and a method for fabricating one or more integrated circuits (ICs). The system includes a plurality of logic tiles formed on a logic wafer and separated by at least one first scribe line, a respective logic tile including a function unit including circuitry configured to perform a respective function; at least one global interconnect configured to communicatively connect the plurality of logic tiles; a plurality of memory tiles formed on a memory wafer connected with the logic wafer, the plurality of memory tiles separated by at least one second scribe line that is substantially aligned with the at least one first scribe line, wherein the logic wafer and the memory wafer are diced along the at least one first scribe line and the at least one second scribe line to obtain a plurality of ICs, a respective IC including at least one logic tile connected with at least one memory tile.

Abstract: An uneven current distribution among a plurality of provided power semiconductor chips is to be suppressed. A power semiconductor module includes a module main body, a plurality of power semiconductor chips arranged on an upper surface of the module main body, and peripheral structures being insulating ferromagnets surrounding parts of a periphery of the module main body in a plan view, in which the plurality of power semiconductor chips are arranged in a vertical direction and a horizontal direction in a plan view, and at least one of the plurality of power semiconductor chips is arranged so as to be surrounded by other power semiconductor chips.

Abstract: An organic light emitting display panel including a first electrode, a second electrode on the first electrode, an organic layer between the first electrode and the second electrode and including at least one light emitting layer, an organic cover layer disposed on the second electrode, a lower layer between the organic cover layer and the second electrode and including a first layer, a second layer, and a third layer, which are different from each other and are sequentially stacked, and an upper layer on the organic cover layer. The first layer contacts the second electrode. The second layer and the third layer each include a silicon compound.

Abstract: A manufacturing method of a semiconductor device includes forming a bitline on a semiconductor structure comprising a conductive feature therein. A spacer is formed adjacent to a sidewall of the bitline, and the spacer has a dielectric contact in a range of about 2 to about 3. A sacrificial layer is formed over the semiconductor structure and covering the spacer. A portion of the sacrificial layer over the bitline is etched to form a first trench to expose a top surface of the bitline. A dielectric layer is formed in the first trench and over the bitline. After forming the dielectric layer, a remaining portion of the sacrificial layer is removed to form a second trench over the semiconductor structure and an outer sidewall of the first spacer is exposed. A contact is formed in the second trench and connected to the conductive feature of the semiconductor structure.

Abstract: A phase change memory device includes a bottom conductive line, a dielectric layer, a bottom memory layer, and a top electrode. The dielectric layer covers the bottom conductive line. The bottom memory layer is in the dielectric layer and is electrically connected to the bottom conductive line. The bottom memory layer includes a tapered portion and a neck portion. The tapered portion is over the bottom conductive line and is tapered toward the bottom conductive line. The neck portion is directly between the tapered portion and the bottom conductive line. The neck portion has a substantially constant width. The top electrode is over and electrically connected to the bottom memory layer.

Abstract: A semiconductor device which has favorable electrical characteristics and can be highly integrated is provided. The semiconductor device includes a first insulator; an oxide over the first insulator; a second insulator over the oxide; a first conductor over the second insulator; a third insulator in contact with a top surface of the first insulator, a side surface of the oxide, a top surface of the oxide, a side surface of the second insulator, and a side surface of the first conductor; and a fourth insulator over the third insulator. The third insulator includes an opening exposing the first insulator, and the fourth insulator is in contact with the first insulator through the opening.

Abstract: A semiconductor device includes a substrate, a passing word line in the substrate, and a dielectric structure surrounding the passing word line. The dielectric structure has an enlargement portion at a bottom of the dielectric structure, and a maximum width of the enlargement portion of the dielectric structure is wider than a width of a top of the dielectric structure.

Abstract: Methods for forming openings in conductive layers and using the same are described. An example method includes: forming a conductive layer; forming a first hard mask on the conductive layer; forming a second hard mask on the first hard mask; providing an opening through the first and second masks; and removing a surface of the conductive layer under the opening. The first hard mask may have hardness greater than hardness of the second hard mask.

Abstract: In a TFT layer provided on a base substrate, a first metal film, a first inorganic insulating film, a second metal film, a second inorganic insulating film, a third metal film, a first flattening film, a fourth metal film, and a second flattening film are sequentially layered. In a frame region, a slit is formed in the second flattening film to surround a display region, a first conductive layer formed by the fourth metal film is provided on the first flattening film exposed from the slit, and a TFT of a drive circuit is provided on the base substrate side of the first conductive layer to overlap with the first conductive layer.

Abstract: A display apparatus includes: a base substrate including a display area, an opening area, and an opening peripheral area between the opening area and the display area, wherein the display area surrounds the opening area, and the opening peripheral area has an annular shape; a conductive pattern disposed on the base substrate in the opening peripheral area and having an annular shape; and a light emitting layer disposed on the base substrate and in a portion of the opening peripheral area, and including an organic material, and wherein the light emitting layer is not formed at a portion of opening peripheral area that is adjacent to the opening area.

Abstract: A method for forming a memory device includes: after a hard mask layer is formed on a semiconductor substrate, a plurality of parallel mask patterns extending along a third direction are formed on the semiconductor substrate by adopting a self-alignment multi- pattern process, an opening is provided between the adjacent mask patterns, and the opening exposes surfaces of a plurality of drain regions and corresponding isolation layers in the third direction.

Abstract: A method for manufacturing an electronic device includes the following steps. A substrate including a first region and a second region is provided. A seed layer is formed on the substrate. A circuit structure layer is formed on the seed layer, and the circuit structure layer has a plurality of first circuit structures disposed on the first region and a plurality of second circuit structures disposed on the second region. The first circuit structures and the second circuit structures are electrically connected through the seed layer. A circuit test process is performed and includes applying a predetermined voltage to the second circuit structures to test the first circuit structures to determine whether the first circuit structures are normal or not.