Abstract: A semiconductor device, a method of fabricating the semiconductor device and a memory are disclosed. In the provided semiconductor device, bit line contact plugs partially reside on insulating material layers in gate trenches in active areas and thus can come into sufficient contact with the active areas. This ensures good electrical transmission between the bit line contact plugs and the active areas even when there are internal voids in the bit line contact plugs. Such bit line contact plugs allowed to contain internal voids can be fabricated in an easier and faster manner, thus allowing a significantly enhanced memory fabrication throughput.

Abstract: The present application discloses a method for fabricating the semiconductor device with the porous decoupling features. The method includes providing a substrate; integrally forming a first conductive line and a bottom contact on the substrate; integrally forming a first conductive line spacer on a sidewall of the first conductive line and a bottom contact spacer on a sidewall of the bottom contact; and forming a porous insulating layer between the first conductive line spacer and the bottom contact spacer.

Abstract: The present disclosure provides a method for fabricating a semiconductor device with a carbon liner over a gate structure. The method includes forming a first gate structure over a semiconductor substrate; forming a first source/drain region in the semiconductor substrate, wherein the first source/drain region is adjacent to the first gate structure; conformally depositing a carbon liner over the first gate structure and the semiconductor substrate; forming a dielectric layer over the carbon liner; and forming a bit line contact penetrating through the dielectric layer and the carbon liner, wherein the bit line contact is electrically connected to the first source/drain region, and wherein the bit line contact is separated from the first gate structure by the carbon liner.

Abstract: A semiconductor structure includes a substrate, a bit line, a dielectric layer and a word line. The substrate has an active area and a trench. The bit line is on the substrate and extends along a direction. The active area includes a first portion and a second portion respectively located at two opposite sides of the bit line and spaced apart from each other along the direction. A landing area extends from the first portion of the active area to the second portion of the active area across the bit line. A dielectric layer is in the trench. The active area is surrounded by the dielectric layer. The word line is surrounded by the dielectric layer. The word line is curved and below the bit line. A portion of the word line is between first and second end portions of the landing area.

Abstract: Disclosed is an electroluminescent display device (100) comprising a plurality of pixels (120) disposed on a substrate (110), each pixel being formed by one or more basic emitting zones (121a, b, c), every basic emitting zone having a base electrode (102a, b, c) disposed on said substrate (110) and an OLED stack (105) comprising an electroluminescent layer disposed on said base electrode (102a, b, c), the device (100) further comprising a common electrode (107) disposed on top of the OLED stack, said device being characterized in that: —two adjacent base electrodes (102a, 102b) belonging to two adjacent basic emitting zones (121a, b) are separated by a filler element having an insulating surface (103) which fills the zone (111) between said adjacent base electrodes (102a, 102b) and electrically insulates them from each other; at least the surface of said filler element having an insulating surface (103) in contact with the base electrodes (102a, 102b) is made of an insulating material; a separator (104) is si

Abstract: A memory device is provided. The memory device includes: a substrate; a memory unit provided on the substrate; a channel provided on the memory unit; a word line surrounded by the channel and extending in a first horizontal direction; a gate insulating layer interposed between the channel and the word line; and a bit line contacting an upper end of the channel and extending in a second horizontal direction that crosses the first horizontal direction.

Abstract: A method of forming a semiconductor structure includes forming a capacitor on a substrate. A recess is formed in the capacitor. A drain region is formed in the recess. A word line is formed on the drain region. A gate structure is formed on the drain region, and the gate structure is electrically connected to the word line. A first bit line is formed on the gate structure, such that the first bit line servers as a source region.

Abstract: A method of manufacturing a memory structure is provided. The method includes forming a first gate structure, a second gate structure, and a plurality of source/drain regions in a substrate, in which the plurality of source/drain regions are disposed on opposite sides of the first gate structure and the second gate structures; performing a dry etching process to form a trench between the first gate structure and the second gate structure; performing a wet etching process to expand the trench, in which the expanded trench has a hexagonal shaped cross section profile; and forming a bit line contact in the expanded trench.

Abstract: Electronic devices and methods of forming electronic devices using a reduced number of hardmask materials and reusing lithography reticles are described. Patterned substrates are formed using a combination of etch selective hardmask materials and reusing reticles to provide a pattern of repeating trapezoidal and rhomboidal openings.

Abstract: The disclosure concerns a resistive memory cell, including a stack of a selector, of a resistive element, and of a layer of phase-change material, the selector having no physical contact with the phase-change material. In one embodiment, the selector is an ovonic threshold switch formed on a conductive track of a metallization level.

Abstract: Disclosed are a display substrate, a preparation method thereof, and a display apparatus. The display substrate includes: a driving substrate, a first electrode, an auxiliary electrode, a pixel definition layer and a hole injection layer. The driving substrate includes a driving circuit and a dielectric layer covering the driving circuit; the first electrode and the auxiliary electrode are on a side of the dielectric layer of the driving substrate away from the driving circuit; the auxiliary electrode at least partially surrounds the first electrode; the pixel definition layer is on a side of the first electrode and the auxiliary electrode away from the driving substrate; the pixel definition layer includes a pixel opening, and the first electrode is at least partially exposed through the pixel opening and is electrically connected to the driving circuit; and the hole injection layer is in the pixel opening and stacked with the first electrode.

Abstract: A capacitive element is located in an active region of the substrate and on a front face of the substrate. The capacitive element includes a first electrode and a second electrode. The first electrode is formed by a first conductive region and the active region. The second electrode is formed by a second conductive region and a monolithic conductive region having one part covering a surface of said front face and at least one part extending into the active region perpendicularly to said front face. The first conductive region is located between and is insulated from the monolithic conductive region and a second conductive region.

Abstract: A display apparatus is disclosed, which may endure deformation by an external force. The display apparatus includes a flexible substrate (110) including a plurality of pores (115); and a pixel array layer (PL) provided on a first surface of the flexible substrate (110), wherein the plurality of pores are (115) provided to be concave from a second surface opposite to the first surface of the flexible substrate (110).

Abstract: Certain aspects of the present disclosure are generally directed to techniques and apparatus for adjusting capacitance in one or more metal-insulator-metal (MIM) capacitors in an effort to reduce capacitance variation between semiconductor devices and improve yield during fabrication. One example method for fabricating a semiconductor device generally includes measuring a capacitance value of a MIM capacitor of the semiconductor device, determining the measured capacitance value of the MIM capacitor is above a target capacitance value for the MIM capacitor, and selectively rupturing a set of connections in the MIM capacitor based on the measured capacitance value. Selectively rupturing the set of connections in the MIM capacitor may reduce the capacitance value of the MIM capacitor to a value approximately that of the target capacitance value.

Abstract: An integrated circuit device includes a fin-type active region protruding from a top surface of a substrate and extending in a first direction parallel to the top surface of the substrate, a gate structure intersecting with the fin-type active region and extending on the substrate in a second direction perpendicular to the first direction, a source/drain region on a first side of the gate structure, a first contact structure on the source/drain region, and a contact capping layer on the first contact structure. A top surface of the first contact structure has a first width in the first direction, a bottom surface of the contact capping layer has a second width greater than the first width stated above in the first direction, and the contact capping layer includes a protruding portion extending outward from a sidewall of the first contact structure.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a magnetic element over the semiconductor substrate. The semiconductor device structure also includes an isolation layer covering the magnetic element and a portion of the semiconductor substrate. The isolation layer contains a polymer material. The semiconductor device structure further includes a conductive line over the isolation layer and extending exceeding edges of the magnetic element.

Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.

Abstract: A three-dimensional (3D) semiconductor memory device including: first and second semiconductor layers horizontally spaced apart from each other; a buried insulating layer between the first and second semiconductor layers; a first cell array structure disposed on the first semiconductor layer, and a second cell array structure disposed on the second semiconductor layer; and an isolation structure disposed on the buried insulating layer between the first and second cell array structures, wherein the first cell array structure includes: an electrode structure including electrodes, which are stacked in a direction perpendicular to a top surface of the first semiconductor layer; and a first source structure disposed between the first semiconductor layer and the electrode structure, the first source structure is extended onto the buried insulating layer, and the isolation structure is between the first source structure of the first cell array structure and a second source structure of the second cell array structur

Abstract: A method for forming a semiconductor device is disclosed. A substrate having a semiconductor substrate, an insulator layer on the semiconductor substrate, and a silicon device layer on the insulator layer is provided. At least one capacitor cavity with corrugated sidewall surface is formed within the insulator layer between the semiconductor substrate and the silicon device layer. At least one buried capacitor is formed in the at least one capacitor cavity. The at least one buried capacitor comprises inner and outer electrodes with a capacitor dielectric layer therebetween. At least one transistor is formed on the substrate. The at least one transistor comprises a source region, a drain region, a channel region between the source region and the drain region, and a gate over the channel region. The source region is electrically connected to the inner electrode of the at least one buried capacitor.

Abstract: Described are light emitting apparatus with self-aligned elements and techniques for manufacturing such light emitting apparatus. In certain embodiments, a method for manufacturing a light emitting apparatus involves forming a plurality of semiconductor layers including a first semiconductor layer, a second semiconductor layer, and a light emission layer between the first semiconductor layer and the second semiconductor layer. The method further involves forming an electrical contact and a spacer. The electrical contact is formed on a surface of the first semiconductor layer. The spacer is formed on the surface of the first semiconductor layer, around the electrical contact. After forming the spacer, the plurality of semiconductor layers is etched to form a mesa with sidewalls that extend from an outer edge of the spacer. The spacer operates as an etch mask that causes the electrical contact to be substantially centered between opposing sidewalls of the mesa.