Patents Examined by Hoal V. Ho
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Patent number: 8411480Abstract: An object is to provide a semiconductor device having a novel structure, which can hold stored data even when not powered and which has an unlimited number of write cycles. A semiconductor device includes a memory cell including a widegap semiconductor, for example, an oxide semiconductor. The memory cell includes a writing transistor, a reading transistor, and a selecting transistor. Using a widegap semiconductor, a semiconductor device capable of sufficiently reducing the off-state current of a transistor included in a memory cell and holding data for a long time can be provided.Type: GrantFiled: April 8, 2011Date of Patent: April 2, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shuhei Nagatsuka, Kiyoshi Kato, Takanori Matsuzaki, Hiroki Inoue
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Patent number: 6388909Abstract: An associative memory includes an array of CAM cells each having a transistor indicating a result from comparing a stored bit with a reference bit. The transistors are connected in serial in each row of the array to form a NAND circuit producing a signal representing that the bits stored in all the cells in the row are consistent with the reference bits or otherwise that the cell at the LSB of the row stores a bit consistent with a reference bit. Each column of the array includes a logic circuit for masking the bits except those continuous from the MSB toward the LSB which correspond to the bits of a word having the most bits continuous from the MSB toward the LSB and consistent with the bits of the reference word among the stored words. The NAND circuit in a row of the cells storing a word having the most bits continuous from the MSB toward the LSB and consistent with the corresponding bits of a reference word develops a signal representing the longest coincidence data detected.Type: GrantFiled: January 9, 2001Date of Patent: May 14, 2002Assignee: Oki Electric Industry Co., Ltd.Inventors: Noriaki Takahashi, Hideaki Odagiri
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Patent number: 6301173Abstract: The present invention is a memory circuit having a plurality of word lines, a plurality of bit line pairs, and memory cells disposed at the cross-position thereof. The memory comprises: a sense amplifier which is shared by the first bit line pair and the second bit line pair disposed in the column direction and amplifies a voltage of the bit line pairs; a first and a second bit line transfer gates which are disposed between the sense amplifier and the first and second bit line pairs, and connects the bit line pair at the selected memory cell side to the sense amplifier; a bit line clamper, which is disposed between the first and second bit line transfer gates, is shared by the first bit line pair and the second bit line pair, and supplies the precharge level to the bit line pairs; and a bit line short circuit, which is disposed at the first and the second bit line pairs respectively and shorts the bit line pairs.Type: GrantFiled: May 10, 1999Date of Patent: October 9, 2001Assignee: Fujitsu LimitedInventors: Shinya Fujioka, Yasuharu Sato
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Patent number: 6219298Abstract: High speed address decoders may include a predecoder and a main decoder that are both responsive to a control signal. The predecoder switches from an active state to an inactive state in response to a transition of the control signal from a first logic state to a second logic state. Conversely, the main decoder commences switching from an inactive state to an active state simultaneously with the transition of the control signal from the first logic state to the second logic state. The predecoder may generate a predecoded address signal while the control signal is in the first logic state, which may then be decoded by the main decoder to activate a line enable signal when the control signal transitions to the second logic state. As a result, address decoding speed may be improved thereby facilitating higher speed operation of an integrated circuit memory device.Type: GrantFiled: January 18, 2000Date of Patent: April 17, 2001Assignee: Samsung Electronics Co., Ltd.Inventors: Nak-won Hur, Byung-sick Moon
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Patent number: 6201724Abstract: A semiconductor memory (100) is disclosed that includes a memory cell array (102) coupled to a register array section (104) that can function as a cache. Access times for misses to the register array section (104) during a continuous read operation can be reduced. A memory cell array (102) is coupled to the register array section (104) by a first transfer bus (TBT1-1 to TBN1-i). First transfer bus (TBT1-1 to TBN1-i) is connected to a local read/write bus (LRWBT and LRWBN) by transistors (106-1 to 108-i) and to register arrays (116-1 to 116-(i+j)) by first switches (118-1 to 118-(i+j)). In a continuous read operation, during a register array section miss, transistors (106-1 to 108-i) are turned on and the first switches (118-1 to 118-(i+j)) are turned on.Type: GrantFiled: November 9, 1999Date of Patent: March 13, 2001Assignee: NEC CorporationInventors: Tatsuya Ishizaki, Misao Suzuki, Souichirou Yoshida
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Patent number: 6195304Abstract: A semiconductor memory device includes a memory cell array having a number of memory cells configured in a square or rectangular formation, the memory cell array having predetermined capacitive loads which are different at different memory locations, the capacitive loads including a smallest capacitive load and a largest capacitive load. A refresh address counter outputs a number of bit signals which constitute a refresh address signal, the refresh address signal indicating an address of a memory cell to be refreshed in the memory device, the bit signals having predetermined high/low-state change periods which are different from each other, the bit signals including a first bit signal corresponding to the smallest capacitive load and a second bit signal corresponding to the largest capacitive load.Type: GrantFiled: February 10, 2000Date of Patent: February 27, 2001Assignee: Fujitsu LimitedInventors: Satoshi Eto, Masato Matsuyima, Kuninori Kawabata, Akira Kikutake
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Patent number: 6157584Abstract: A redundancy configurations is described in which a redundant element is able to overpower a defective element without the need for physical disconnection or logical deselection and in which plural redundant rows (or columns) are provided to replace more than one defective row (or column) in an array or subarray. Redundancy configurations are further described in which a redundant element is able to overpower a defective element without the need for physical disconnection or logical deselection and in which a given redundant row (or column) may replace a defective row (or column) in one of plural subarrays representing distinct sets of rows (or columns).Type: GrantFiled: May 20, 1999Date of Patent: December 5, 2000Assignee: Advanced Micro Devices, Inc.Inventor: John Christian Holst
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Patent number: 6147894Abstract: A data storage device including a substrate, a data storage layer on the substrate, and a spin-polarized electron source. The data storage layer comprises a fixed number of atomic layers of a magnetic material which provide the data storage layer with a magnetic anisotropy perpendicular to a surface of the data storage layer. A data magnetic field is created in the data storage layer. The data magnetic field is polarized either in a first direction corresponding to a first data value or in a second direction corresponding to a second data value.Type: GrantFiled: September 21, 1998Date of Patent: November 14, 2000Assignee: TeraStore, Inc.Inventor: Thomas D. Hurt
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Patent number: 6137718Abstract: In order to increase the storage density, in a memory cell arrangement having MOS transistors as memory cells which has as gate dielectric, a dielectric triple layer having a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer, the silicon oxide layers each having a thickness of at least 3 nm, the information is stored using multi-value logic with up to 2.sup.6 values. In this case, use is made of the fact that these memory cells have a time period greater than 1000 years for data retention and their threshold voltage has a very small drift.Type: GrantFiled: January 28, 1999Date of Patent: October 24, 2000Assignee: Siemens AktiengesellschaftInventor: Hans Reisinger
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Patent number: 6097642Abstract: In a memory system, sense amplifiers are connected to a memory cell array for driving a number of read bus lines according to data read from the memory cell array at periodic intervals. A number of midpoint holding circuits are associated respectively with the read bus lines. Each of the midpoint holding circuits comprises a pull-up driver and a pull-down driver connected in series between terminals of high and low voltages, a circuit node between the drivers being connected to the associated bus line, the drivers having a substantially equal threshold voltage. Control circuitry is responsive to a midpoint control pulse for causing one of the drivers to turn on depending on a voltage at the bus line, so that the conducting driver automatically turns off when the bus line attains a midpoint level between the high and low voltages during an interval when the bus line is not driven by the sense amplifiers.Type: GrantFiled: March 22, 1999Date of Patent: August 1, 2000Assignee: NEC CorporationInventor: Hiroyuki Takahashi
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Patent number: 6046934Abstract: A method and device for programming multiple levels of voltage states in a memory cell. A program and verify memory cell device includes a memory cell coupled with at least one dummy cell, the devices sharing common drain, gate, and source nodes. The threshold voltage of each dummy cell is set to a target threshold level for programming the memory cell. A stair-step sequence of pulses is used to program and verify the memory cell. A constant current source can also be coupled between the source node and the ground. The programming steps for this device include applying a high voltage to the drain and gate nodes, and coupling the source to level while starting the program pulse, then establishing a constant current at the source to pull it from high to level, and then applying program and verify pulses at the memory cell gate.Type: GrantFiled: January 12, 1999Date of Patent: April 4, 2000Assignee: Macronix International Co., Ltd.Inventor: Chin Hsi Lin
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Patent number: 6026034Abstract: Switching transistors 20, 22, 22P, 21, 23 and 23P and a portion of control circuit for transistors 20 and 21 constitutes a bit line reset circuit on memory cell side. In reading `H` from the memory cell connected to a bit line BLC or *BLC, the both bit lines are set at a higher reset potential Vii, while in reading `L`, the both bit lines are reset at a lower reset potential Vss. Transfer gates 10 and 11 are turned off before sufficient amplification of a potential difference between the bit lines BL and *BL. The operation of restoring into a memory cell read destructively from is performed in parallel with the operation of bit line reset.Type: GrantFiled: May 7, 1998Date of Patent: February 15, 2000Assignee: Fujitsu LimitedInventors: Takaaki Suzuki, Shinya Fujioka, Yasuharu Sato
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Patent number: 5999462Abstract: An analog delay circuit which includes an analog memory circuit wherein a plurality of memory cells each including a memory capacitor and a selection switch for the memory capacitor are arranged in a matrix includes row switches provided for the individual columns for individually being driven by row selection signals. A same clock signal from a clock generation circuit is supplied commonly to an X direction scanning circuit and a Y direction scanning circuit. The number of stages of registers of the X direction scanning circuit and the number of stages of registers of the Y direction scanning circuit are set so that they have no common divisor other than 1. Consequently, when the memory cells are to be selectively scanned, a same selection condition can be provided to all of the memory cells without relying upon the positions of the memory cells, and the parasitic capacitance connected to a signal write/read terminal is reduced.Type: GrantFiled: December 4, 1998Date of Patent: December 7, 1999Assignee: Sony CorporationInventors: Masayuki Katakura, Masashi Takeda
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Patent number: 5850361Abstract: A coding device including an array of multibit registers, each being composed of a plurality of programmable nonvolatile memory cells connected to an OR configuration to a common sensing line of the register to which a single reading circuit is associated. A first, select/enable bus (SELbus) controls the connection of only one at a time of said programmable memory cells to said common sensing line of each multibit register. To each wire of a second, configuring bus (CODE bus) are connected in common the current terminals of as many programming transistors as the memory cells that compose each register, and to each wire of a third, contingently programming bus (PG bus) are connected the gates of the programming transistors of memory cells of the same order of said registers.Type: GrantFiled: April 4, 1996Date of Patent: December 15, 1998Assignee: SGS-Thomson Microelectronics S.r.l.Inventor: Luigi Pascucci
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Patent number: 5825691Abstract: A start write sensing circuit for sensing a start of a write is coupled to a write simulation circuit. The write simulation circuit preferably includes a memory cell replicate to mimic the amount of time required for writing data to the memory cell. The state of the data stored in the memory cell replicate is changed upon the write sensing circuit sensing the start of a write. The memory cell replicate is preferably constructed using the same structure, design, and process as the memory cells of the array so as to accurately simulate the time required for writing data to a memory cell in the array. Upon the write to the memory cell replicate being completed, a write termination signal is generated for terminating the write signal. The write termination signal also is a reset signal for resetting circuits of the array to prepare for the next cycle, whether it be a read or a write.Type: GrantFiled: May 19, 1997Date of Patent: October 20, 1998Assignee: STMicroelectronics, Inc.Inventor: David C. McClure
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Patent number: 5740097Abstract: A timing control signal SR is made low to switch on a P-MOSFET and switch off an N-MOSFET, and with an N-MOSFET as a boundary, a voltage V.sub.MATCHI on the side of a NOT circuit of a match-line is pulled up to a power supply voltage V.sub.DD. During this, a comparison operation is done in a content addressable memory cell, and an N-MOSFET is switched on or off according to the result of comparison. Next, the control signal SR goes to a logic high level, so the P-MOSFET is switched off and the N-MOSFET is switched on. As a result, if the N-MOSFET is on, the voltages V.sub.MATCHI and V.sub.MATCH will be reduced to a ground level, but the through current is prevented because the P-MOSFET is off. If the N-MOSFET is off, the V.sub.MATCH will be pulled up to V.sub.DD -V.sub.tn (V.sub.tn is the threshold voltage of the N-MOSFET), the V.sub.MATCHI will be held to V.sub.DD by the NOT circuit and the P-MOSFET, and a signal representative of a result of comparison will be output from the NOT circuit.Type: GrantFiled: November 28, 1995Date of Patent: April 14, 1998Assignee: International Business Machines CorporationInventor: Akashi Satoh