Patents Examined by Hoang-Quan Ho
  • Patent number: 10964830
    Abstract: A surface plasmon-semiconductor heterojunction resonant optoelectronic device and a preparation method thereof are provided. A surface ligand molecule is modified on a plasmonic nanostructure, a plasmonic crystal face structure is bound to the surface ligand molecule, a semiconductor nanostructure seed crystal is located on the plasmonic crystal face structure, a one-dimensional semiconductor nanostructure is located on the semiconductor nanostructure seed crystal, and all parts are in tight contact. The heterogeneous integration material achieves a lattice match at an interface, greatly reduces a loss caused by defects and rough crystal faces, and can achieve direct coupling of a surface plasmon mode and an optical mode. The heterogeneous integration material has a large application prospect in the fields of a nanolaser, a nano heat source and photoelectric detection and photocatalysis.
    Type: Grant
    Filed: May 28, 2018
    Date of Patent: March 30, 2021
    Assignee: SOUTHEAST UNIVERSITY
    Inventors: Tong Zhang, Shanjiang Wang, Xiaoyang Zhang
  • Patent number: 10964781
    Abstract: The present disclosure, in some embodiments, relates to a high voltage resistor device. The device includes a buried well region disposed within a substrate and having a first doping type. A drift region is disposed within the substrate and contacts the buried well region. The drift region has the first doping type. A body region is disposed within the substrate and has a second doping type. The body region laterally contacts the drift region and vertically contacts the buried well region. An isolation structure is over the drift region and a resistor structure is over the isolation structure.
    Type: Grant
    Filed: November 26, 2018
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Cheng Chiu, Wen-Chih Chiang, Chun Lin Tsai, Kuo-Ming Wu, Shiuan-Jeng Lin, Yi-Min Chen, Hung-Chou Lin, Karthick Murukesan
  • Patent number: 10964621
    Abstract: Methods, systems, and devices for a memory device with a high resistivity thermal barrier are described. In some examples a barrier material may be positioned over a memory cell region, an oxide region, and/or a through-silicon via (TSV). The barrier may include a first region above the memory cell region and a second region above the TSV. A process, such as a plasma treatment, may be applied to the barrier, which may result in the first and second regions having different thermal resistivities (e.g., different densities). Accordingly, due to the different thermal resistivities, the memory cells may be thermally insulated from thermal energy generated in the memory device.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: March 30, 2021
    Assignee: Micron Technology, Inc.
    Inventors: David Ross Economy, Pengyuan Zheng
  • Patent number: 10957659
    Abstract: A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.
    Type: Grant
    Filed: May 23, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kenneth Rodbell, Davood Shahrjerdi
  • Patent number: 10930896
    Abstract: The present invention provides a package method of an OLED element and an OLED package structure. In the package method of the OLED element, according to the present invention, by manufacturing a circle of the retaining wall at the periphery of the OLED element, and then forming the laminated film covering the OLED element in the region surrounded by the retaining wall, and the laminated film comprises the few first barrier layers and the few buffer layers which are alternately stacking, and ultimately, forming the second barrier layer which completely covers the buffer layer and the top of the retaining wall on the outermost buffer layer of the laminated film, the OLED package structure of extremely strong sealing can be obtained. In the package method, a protective shield of extremely strong sealing for the OLED element is formed with the retaining wall and the outermost second barrier layer.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: February 23, 2021
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jiajia Qian
  • Patent number: 10910582
    Abstract: A light emitting display device and a method of manufacturing a light emitting display device, the device including a substrate; a switching element on the substrate; a first electrode connected to the switching element; a second electrode on the first electrode; a light emitting element between the first electrode and the second electrode; and a non-conductive oxide film between the first electrode and the light emitting element.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: February 2, 2021
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Gwuihyun Park, Pilsoon Hong, Chulwon Park, Bogeon Jeon
  • Patent number: 10903371
    Abstract: According to one embodiment, an apparatus includes a substrate, and at least one three dimensional (3D) structure above the substrate. The substrate and the 3D structure each include a semiconductor material. The 3D structure also includes: a first region having a first conductivity type, and a second region coupled to a portion of at least one vertical sidewall of the 3D structure.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: January 26, 2021
    Assignees: Lawrence Livermore National Security, LLC, The Regents of the University of California
    Inventors: Adam Conway, Sara Elizabeth Harrison, Rebecca J. Nikolic, Qinghui Shao, Lars Voss, Srabanti Chowdhury
  • Patent number: 10840358
    Abstract: Semiconductor structures and method for forming the same are provide. The method includes forming a gate structure over a substrate and forming a recess in the substrate adjacent to the gate structure. The method further includes forming a doped region at a sidewall and a bottom surface of the recess and partially removing the doped region to modify a shape of the recess. The method further includes forming a source/drain structure over a remaining portion of the doped region.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shahaji B. More, Shih-Chieh Chang, Cheng-Han Lee, Huai-Tei Yang
  • Patent number: 10840192
    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a stiffener to improve a package substrate against out of plane deformation. In one example, a chip package assembly is provided that includes a package substrate, at least one integrated circuit (IC) die and a stiffener. The package substrate has a first surface and a second surface coupled by a side wall. The at least one IC die is disposed on the first surface of the package substrate. The stiffener is disposed outward of the at least one IC die. The stiffener has a first surface disposed outward of and bonded to the side wall of the package substrate. The stiffener has a second surface bonded to at least one of the first and second surfaces of the package substrate.
    Type: Grant
    Filed: April 6, 2017
    Date of Patent: November 17, 2020
    Assignee: XILINX, INC.
    Inventors: Nael Zohni, Shin S. Low, Inderjit Singh, Raghunandan Chaware, Ganesh Hariharan
  • Patent number: 10833123
    Abstract: A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.
    Type: Grant
    Filed: January 15, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Bahman Hekmatshoartabari, Chung H. Lam, Fabio Carta, Matthew J. BrightSky
  • Patent number: 10825821
    Abstract: A computing device includes a wafer having multiple layers, the wafer including a top layer and sublayers disposed below it, the sublayers including one or more memory devices. The computing device also includes two or more shaped retainer elements shaped to mate with and at least partially surround at least the top of the wafer and in electrical contact with one or more chips disposed on a top of the top layer and a holding device that mates with the retainer elements to provide at least power to the retaining elements. So arranged, the wafer may be cooled.
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: November 3, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Babar A. Khan, Arvind Kumar, Kamal K. Sikka
  • Patent number: 10825966
    Abstract: A display panel, a display device and a display method are provided. The display panel includes a base substrate, a pixel array and a light conversion layer. The pixel array is arranged on the base substrate and includes a plurality of pixel units, and the light conversion layer is arranged on a display side of the pixel array. Each of the plurality of pixel units includes an optical resonant structure, and the optical resonant structure includes a first reflection layer, a second reflection layer and a dielectric layer. The first reflection layer is arranged on the base substrate, the second reflection layer is arranged on the first reflection layer and is parallel to the first reflection layer, and the dielectric layer is arranged between the first reflection layer and the second reflection layer.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: November 3, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Zhidong Wang, Lianjie Qu, Yun Qiu
  • Patent number: 10818866
    Abstract: An organic electroluminescent device, a production method thereof, and a display apparatus are disclosed. Specifically, the organic electroluminescent device includes: a substrate; a pixel defining layer on the substrate; and a hole injection layer on the substrate, wherein the hole injection layer is located in a pixel defining opening of the pixel defining layer, wherein the hole injection layer includes a first hole injection sub-layer and a second hole injection sub-layer covering the first hole injection sub-layer, an orthographic projection area of the second hole injection sub-layer on the substrate is greater than the orthographic projection area of the first hole injection sub-layer on the substrate, and a hole mobility of the second hole injection sub-layer is greater than the hole mobility of the first hole injection sub-layer.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: October 27, 2020
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventor: Wenjun Hou
  • Patent number: 10811421
    Abstract: Vertical memory devices, and methods of manufacturing the same, include providing a substrate including a cell array region and a peripheral circuit region, forming a mold structure in the cell array region, forming an opening for a common source line passing through the mold structure and extending in a first direction perpendicular to a top surface of the substrate, forming a first contact plug having an inner sidewall delimiting a recessed region in the opening for the common source line, and forming a common source bit line contact electrically connected to the inner sidewall of the first contact plug.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: October 20, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-yong Park, Kee-jeong Rho, Hyeong Park, Tae-wan Lim
  • Patent number: 10798496
    Abstract: A hearing assistance device to provide sound to the ear of a user, the device comprising a housing, hearing assistance electronics enclosed in the housing, an acoustic transducer adapted to be worn in the ear, a cable assembly adapted to connect the acoustic transducer to the hearing assistance electronics, a wireless communications receiver connected to the hearing assistance electronics, and an antenna comprising one or more conductors forming at least a portion of the cable assembly.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: October 6, 2020
    Assignee: Starkey Laboratories, Inc.
    Inventor: Jeffrey Paul Solum
  • Patent number: 10784468
    Abstract: The present invention provides a package method of an OLED element and an OLED package structure. In the package method of the OLED element, according to the present invention, by manufacturing a circle of the retaining wall at the periphery of the OLED element, and then forming the laminated film covering the OLED element in the region surrounded by the retaining wall, and the laminated film comprises the few first barrier layers and the few buffer layers which are alternately stacking, and ultimately, forming the second barrier layer which completely covers the buffer layer and the top of the retaining wall on the outermost buffer layer of the laminated film, the OLED package structure of extremely strong sealing can be obtained. In the package method, a protective shield of extremely strong sealing for the OLED element is formed with the retaining wall and the outermost second barrier layer.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: September 22, 2020
    Assignee: TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Jiajia Qian
  • Patent number: 10777673
    Abstract: A high electron mobility transistor (HEMT) gallium nitride (GaN) bidirectional blocking device includes a hetero-junction structure comprises a first semiconductor layer interfacing a second semiconductor layer of two different band gaps thus generating an interface layer as a two-dimensional electron gas (2DEG) layer. The HEMT GaN bidirectional blocking device further includes a first source/drain electrode and a second source/drain electrode disposed on two opposite sides of a gate electrode disposed on top of said hetero-junction structure for controlling a current flow between the first and second source/drain electrodes in the 2DEG layer wherein the gate electrode is disposed at a first distance from the first source/drain electrode and a second distance from the second source/drain electrode and the first distance is different from the second distance.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 15, 2020
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventor: David Sheridan
  • Patent number: 10777583
    Abstract: An array substrate, a method for manufacturing the same and a display panel are provided. The array substrate comprises: a substrate; a bare chip fixed on the substrate, the bare chip comprising pins; a buffer layer and a first metallic layer disposed sequentially on the bare chip, the first metallic layer comprising outer leads in one-to-one correspondence with the pins of the bare chip, the outer leads being connected electrically to the pins corresponding thereto of the bare chip, and the outer leads being electrically insulated from each other; a thin film transistor; and a first signal wire and a first connecting wire disposed in a same layer as a gate electrode of the thin film transistor, and a second signal wire and a second connecting wire disposed in a same layer as a source electrode and a drain electrode of the thin film transistor.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: September 15, 2020
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., BEIJING BOE DISPLAY TECHNOLOGY CO., LTD.
    Inventors: Zhidong Wang, Yun Qiu, Lianjie Qu
  • Patent number: 10741560
    Abstract: A semiconductor device includes a source region and a drain region formed in a transistor structure. A channel region is disposed between the source region and the drain region. A cladding layer is formed on the channel region, the cladding layer including a semiconductor material. A gate dielectric of a gate structure is formed on the cladding layer.
    Type: Grant
    Filed: October 26, 2017
    Date of Patent: August 11, 2020
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 10727327
    Abstract: Fabrication methods and device structures for a silicon controlled rectifier. A cathode is arranged over a top surface of a substrate and a well is arranged beneath the top surface of the substrate. The cathode is composed of a semiconductor material having a first conductivity type, and the well also has the first conductivity type. A semiconductor layer, which has a second conductivity type opposite to the first conductivity type, includes a section over the top surface of the substrate. The section of the semiconductor layer is arranged to form an anode that adjoins the well along a junction.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 28, 2020
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Rahul Mishra, Vibhor Jain, Ajay Raman, Robert J. Gauthier