Patents Examined by Hoang-Quan Ho
  • Patent number: 10529698
    Abstract: An embodiment is a package including a first package structure. The first package structure includes a first integrated circuit die having an active side and a back-side, the active side comprising die connectors, a first electrical connector adjacent the first integrated circuit die, an encapsulant laterally encapsulating the first integrated circuit die and the first electrical connector, a first redistribution structure on and electrically connected to the die connectors of the first integrated circuit die and the first electrical connector, and thermal elements on the back-side of the first integrated circuit die. The package further includes a second package structure bonded to the first electrical connector and the thermal elements with a first set of conductive connectors.
    Type: Grant
    Filed: September 1, 2017
    Date of Patent: January 7, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Hua Yu, Der-Chyang Yeh, Han-Ping Pu
  • Patent number: 10256271
    Abstract: A method for deactivating memory cells affected by the presence of grain boundaries in polycrystalline selection devices includes crystallizing a semiconductor layer in a diode stack to form a polycrystalline layer for selection diodes formed in a crossbar array. To achieve a crystalline state in phase change memory elements coupled to corresponding selection diodes perform an anneal. Memory cells having shunted selection diodes due to grain boundaries are identified by scanning the array using sense voltages. A second voltage larger than the sense voltages is applied to the phase change memory elements gated by the shunted selection diodes such that the phase change memory elements gated by the shunted diodes achieve a permanently high resistive state.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bahman Hekmatshoartabari, Chung H. Lam, Fabio Carta, Matthew J. BrightSky
  • Patent number: 10236214
    Abstract: A method of forming a vertical transistor includes forming a first pair of fins on a substrate; forming a second pair of fins on the substrate; forming a first trench in the substrate and interposed between each one of the first pair of fins; forming a second trench in the substrate and interposed between each one of the second pair of fins, wherein the second trench is deeper than the first trench; forming a first semiconductor structure interposed between each one of the first pair of fins, the first semiconductor structure having a first gate region interposed between a first source region and a first drain region; and forming a second semiconductor structure interposed between each one of the second pair of fins, the second semiconductor structure having a first gate region interposed between a second source region and a second drain region.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: March 19, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Xin Miao, Wenyu Xu, Chen Zhang
  • Patent number: 10229919
    Abstract: A vertical field effect transistor (FET) includes a vertical semiconductor channel having a first end that contacts an upper surface of a substrate and an opposing second end that contacts a source/drain region. An electrically conductive gate encapsulates the vertical semiconductor channel. The vertical FET further includes a split-channel antifuse device between the source/drain region and the electrically conductive gate. The split-channel antifuse device includes a gate dielectric having a thickness that varies between the source/drain region and the electrically conductive gate.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: March 12, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Juntao Li, Geng Wang, Qintao Zhang
  • Patent number: 10224463
    Abstract: An object of the present invention is to provide a film formation technique having high productivity by realizing a foundation layer having excellent crystallinity with a small film thickness of about 2 ?m. An embodiment of the present invention relates to a film forming method which includes the step of forming a buffer layer by sputtering on a sapphire substrate held by a substrate holder. The buffer layer includes an epitaxial film having a wurtzite structure prepared by adding at least one substance selected from the group consisting of C, Si, Ge, Mg, Zn, Mn, and Cr to AlxGa1?xN (where 0?x?1).
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: March 5, 2019
    Assignee: CANON ANELVA CORPORATION
    Inventor: Yoshiaki Daigo
  • Patent number: 10204897
    Abstract: An ESD protection semiconductor device includes a substrate, a gate set formed on the substrate, a source region and a drain region formed in the substrate respectively at two sides of the gate set, and at least a doped region formed in the source region. The source region and the drain region include a first conductivity type, and the doped region includes a second conductivity type complementary to the first conductivity type. The doped region is electrically connected to a ground potential.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: February 12, 2019
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Chung-Yu Huang, Kuan-Cheng Su, Tien-Hao Tang, Ping-Jui Chen, Po-Ya Lai
  • Patent number: 10176987
    Abstract: A SiC epitaxial wafer including: a SiC epitaxial layer that is formed on a SiC substrate having an off angle, wherein the surface density of triangular defects, in which a distance from a starting point to an opposite side in a horizontal direction is equal to or greater than (a thickness of the SiC epitaxial layer/tan(x))×90% and equal to or less than (the thickness of the SiC epitaxial layer/tan(x))×110%, in the SiC epitaxial layer is in the range of 0.05 pieces/cm2 to 0.5 pieces/cm2 (where x indicates the off angle).
    Type: Grant
    Filed: May 4, 2017
    Date of Patent: January 8, 2019
    Assignee: SHOWA DENKO K.K.
    Inventors: Akira Miyasaka, Yutaka Tajima, Yoshiaki Kageshima, Daisuke Muto, Kenji Momose
  • Patent number: 10170575
    Abstract: A method of fabricating the vertical field effect transistor includes forming a dielectric layer on a metal semiconductor alloy layer that is present on a substrate of a semiconductor material. The dielectric layer is bonded to a supporting substrate. The substrate of the semiconductor material is cleaved, wherein a remaining portion of the semiconductor material provides a semiconductor surface layer in direct contact with the metal semiconductor alloy layer. A vertical fin type field effect transistor (FinFET) is formed atop the stack of the semiconductor surface layer, the metal semiconductor alloy layer, the dielectric layer and the supporting substrate, wherein the semiconductor surface layer provides at least one of a source region or a drain region of the FinFET and the metal semiconductor alloy provides a contact to the source region or the drain region of the FinFET.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Tak H. Ning, Alexander Reznicek
  • Patent number: 10158062
    Abstract: A method is provided of forming a superconductor device interconnect structure. The method includes forming a first high temperature dielectric layer overlying a substrate, forming a base electrode in the first high temperature dielectric layer with the base electrode having a top surface aligned with the top surface of the first high temperature dielectric layer, and depositing a second high temperature dielectric layer over the first high temperature dielectric layer and the base electrode. The method further comprises forming a first contact through the second dielectric layer to a first end of the base electrode, forming a Josephson junction (JJ) overlying and in contact with the first contact, and forming a second contact through the second dielectric layer to a second end of the base electrode.
    Type: Grant
    Filed: May 4, 2018
    Date of Patent: December 18, 2018
    Assignee: NORTHROP GRUMMAN SYSTEMS CORPORATION
    Inventors: Christopher F. Kirby, Michael Rennie, Aurelius L. Graninger
  • Patent number: 10115729
    Abstract: An anti-fuse nonvolatile memory device includes an anti-fuse memory cell and a bipolar junction transistor. The anti-fuse, memory cell has a first terminal and a second terminal. The second terminal is coupled to a word line. The bipolar junction transistor has a collector terminal coupled to the first terminal of the anti-fuse, memory cell, a base terminal, and an emitter terminal coupled to a bit line.
    Type: Grant
    Filed: August 25, 2016
    Date of Patent: October 30, 2018
    Assignee: SK Hynix Inc.
    Inventor: Kwang II Choi
  • Patent number: 10109688
    Abstract: The present invention provides a repair structure of a line defect of an AMOLED display panel and a repair method. The conductive film (410) correspondingly overlaps and covers above the test TFT (310) and is insulated from the test TFT (310), and the repair line (420) is insulated and crossed with all the signal fanout lines (200) and the corresponding test line (330). It is realized that the repair line is directly grafted on the AMOLED display panel detecting circuit, which can utilize the present detecting circuit layout of the AMOLED display panel capable of introducing the repair line for having the repair function and saving the layout space, and has no additional requirement to the control IC, and particularly, can be applicable for the line defect repair of the small size, high resolution AMOLED display panel.
    Type: Grant
    Filed: April 25, 2016
    Date of Patent: October 23, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Baixiang Han
  • Patent number: 10104797
    Abstract: A power module includes a heat-dissipating substrate, a first planar power device and a second planar power device. The first planar power device includes a plurality of electrodes disposed on an upper surface of the first planar power device. The second planar power device includes a plurality of electrodes disposed on an upper surface of the second planar power device. Lower surfaces of the first planar power device and the second planar power device are disposed on the heat-dissipating substrate.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: October 16, 2018
    Assignee: DELTA ELECTRONICS (SHANGHAI) CO., LTD.
    Inventor: Jian-Hong Zeng
  • Patent number: 10079199
    Abstract: A through-substrate vias structure includes a substrate having opposing first and second major surfaces. One or more conductive via structures are disposed extending from the first major surface to a first vertical distance within the substrate. A recessed region extends from the second major surface to a second vertical distance within the substrate and adjoining a lower surface of the conductive via. In one embodiment, the second vertical distance is greater than the first vertical distance. A conductive region is disposed within the recessed region and is configured to be in electrical and/or thermal communication with the conductive via.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: September 18, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Michael J. Seddon, Francis J. Carney
  • Patent number: 10050030
    Abstract: A semiconductor device includes a FinFET component, a plurality of patterned dummy semiconductor fins arranged aside a plurality of fins of the FinFET component, an isolation structure formed on the patterned dummy semiconductor fins, and a tuning component formed on the patterned dummy semiconductor fins and electrically connected to the FinFET component. A height of the patterned dummy semiconductor fins is shorter than that of the fins of the FinFET component.
    Type: Grant
    Filed: January 7, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Chien Huang, Chi-Wen Liu, Horng-Huei Tseng, Tsung-Yu Chiang
  • Patent number: 10050077
    Abstract: A device including a substrate and an imaging element layer having a plurality of imaging elements is provided, where the imaging element layer is located between the substrate and a wiring layer having a plurality of wiring lines (41), and wiring lines of the wiring layer are arranged in pixel regions (Z) configured to receive light having a wavelength less than a predetermined wavelength (B, G). Accordingly, by more uniformly distributing the wiring layer throughout, it is possible to reduce an unevenness that occurs at a polishing film. Moreover, because wiring lines are not disposed in pixel regions (Z) configured to receive light having a wavelength greater than the predetermined wavelength (R), irregularities may be reduced.
    Type: Grant
    Filed: July 22, 2014
    Date of Patent: August 14, 2018
    Assignee: Sony Corporation
    Inventor: Tadahiro Hagita
  • Patent number: 10038074
    Abstract: The present invention provides a manufacture method of a TFT substrate and a manufactured TFT substrate. By locating the first channel region and the first lightly doped offset region between the first source and the drain, and locating the second channel region and the second lightly doped offset region between the second source and the drain, and forming the first overlapping region and the second overlapping region respectively between the drain and the gate and between the second source and the gate, thus, the paths of the current flowing from the first, the second sources to the drain and the current flowing from the drain to the first, the second sources are the same. Namely, the current path from source to the drain and the current path from the drain to the source are the same. According, the symmetry of the TFT structure is realized.
    Type: Grant
    Filed: April 26, 2016
    Date of Patent: July 31, 2018
    Assignee: SHENZHEN CHINA STAR OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventor: Shipeng Chi
  • Patent number: 10038124
    Abstract: Provided is a light-emitting device that has excellent light extraction efficiency, inhibits deterioration of light-emission characteristics over time, and can be easily produced. The light-emitting device includes a substrate, a solid-state light-emitting element mounted on the substrate, a circular tube-shaped member positioned on the substrate such as to surround the solid-state light-emitting element, and a transparent resin portion including a cylindrical section that encapsulates the solid-state light-emitting element and that is in contact with an inner surface of the circular tube-shaped member, and a dome-shaped section that is positioned above the cylindrical section. The inner surface of the circular tube-shaped member is water repellent. The dome-shaped section contains a phosphor that is excited by light of a light-emission wavelength of the solid-state light-emitting element.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: July 31, 2018
    Assignee: Dexerials Corporation
    Inventor: Takehiro Yamasuge
  • Patent number: 10038133
    Abstract: Sensor including a substrate, an assembly of thermoelectric layers including at least one first and one second junction of a thermocouple, at least one first and one second connection pads arranged to transfer heat respectively to each first and each second junction, a support member (2) of the substrate (3) intended to be connected to the hot source (Sc) and to the cold source (Sf), first and second metal connectors arranged to electrically connect the support member (2) respectively to each first and each second connection pad, the support member (2) including a thermal conductor configured to transfer heat from the hot source (Sc) to the first metal connector, and to transfer heat from the second metal connector to the cold source (Sf).
    Type: Grant
    Filed: December 18, 2015
    Date of Patent: July 31, 2018
    Assignees: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, HOTBLOCK ONBOARD
    Inventors: Guillaume Savelli, Joël Dufourcq
  • Patent number: 10014377
    Abstract: An electrical device comprising a base semiconductor layer of a silicon including material; a dielectric layer present on the base semiconductor layer; a first III-V semiconductor material area present in a trench in the dielectric layer, wherein a via of the III-V semiconductor material extends from the trench through the dielectric layer into contact with the base semiconductor layer; a second III-V semiconductor material area present in the trench in the dielectric layer wherein the second III-V semiconductor material area does not have a via extending through the dielectric layer into contact with the base semiconductor layer; and a semiconductor device present on the second III-V semiconductor material area, wherein the first III-V semiconductor material area and the second III-V semiconductor material area are separated by a low aspect ratio trench extending to the dielectric layer.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: July 3, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng-Wei Cheng, Edward William Kiewra, Amlan Majumdar, Devendra K. Sadana, Kuen-Ting Shiu, Yanning Sun
  • Patent number: 10008516
    Abstract: The present disclosure relates to the field of TFT manufacturing process, and provides an LTPS TFT array substrate, its manufacturing method and a display device. The LTPS TFT array substrate includes contact holes through which a source electrode and a drain electrode of the array substrate are connected to an active layer, respectively, wherein a conductive pattern connected to the active layer is provided at a base portion of the contact hole. According to the present disclosure, it is able to form an excellent ohmic contact between the source/drain electrodes and the active layer after the contact holes have been etched, thereby to ensure the display quality of the display device.
    Type: Grant
    Filed: July 16, 2014
    Date of Patent: June 26, 2018
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Yueping Zuo, Zheng Liu