Patents Examined by Hoang-Quan Ho
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Patent number: 11527671Abstract: An optical package structure includes a substrate, an emitter, a first detector and a light-absorption material. The substrate has a first surface and a second surface opposite to the first surface, the substrate includes a via defining a third surface extending from the first surface to the second surface. The emitter is disposed on the first surface of the substrate. The first detector is disposed on the first surface and aligned with the via of the substrate. The light-absorption material is disposed on the third surface of the substrate.Type: GrantFiled: December 31, 2019Date of Patent: December 13, 2022Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chi Sheng Tseng, Hui-Chung Liu, Ching-Han Huang
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Patent number: 11508866Abstract: A photoelectric conversion element for detecting the spot size of incident light. The photoelectric conversion element includes a photoelectric conversion substrate having two principal surfaces, and comprises a first sensitive part and a second sensitive part that have mutually different photoelectric conversion characteristics. When a sensitive region appearing in the principal surface of the first sensitive part is defined as a first sensitive region, and a sensitive region appearing in the principal surface of the second sensitive part is defined as a second sensitive region, the first sensitive region is configured to receive at least a portion of light incident on a light-receiving surface and to decrease, proportionally to enlargement in an irradiation region of the principal surface irradiated with the incident light, the ratio of the first sensitive region to the second sensitive region in the irradiation region.Type: GrantFiled: February 7, 2020Date of Patent: November 22, 2022Assignee: KANEKA CORPORATIONInventors: Kunta Yoshikawa, Takashi KuchIyama
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Patent number: 11502224Abstract: A semiconductor body main include a III-V compound semiconductor material having a p-conductive region doped with a p-dopant. The p-conductive region may include at least one first section, one second section, and one third section. The second section may be arranged between the first and third sections. The second section may directly adjoin the first and third sections. An indium concentration of at least one of the sections differs from an indium concentration of the other two sections.Type: GrantFiled: June 14, 2018Date of Patent: November 15, 2022Assignee: OSRAM OPTO SEMICONDUCTORS GMBHInventors: Ingrid Koslow, Massimo Drago, Joachim Hertkorn, Alexander Frey
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Patent number: 11495706Abstract: A method for producing an optoelectronic component and an optoelectronic component are disclosed. In an embodiment a method includes providing an optoelectronic semiconductor chip with a radiation passage surface on a connection carrier, applying a deformable spacer to the radiation passage surface of the semiconductor chip, inserting the connection carrier with the semiconductor chip into a cavity of a tool, deforming, by the tool, the deformable spacer and encapsulating the semiconductor chip with a casting compound.Type: GrantFiled: August 28, 2018Date of Patent: November 8, 2022Assignee: OSRAM OLED GMBHInventor: Michael Mueller
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Patent number: 11476374Abstract: A sensor device provided in the disclosure includes a sensor substrate, a first transparent layer, a collimator layer, and a lens. The first transparent layer is disposed on the sensor substrate, wherein the first transparent layer defines an alignment structure. The collimator layer is disposed on the first transparent layer. The lens is disposed on the collimator layer.Type: GrantFiled: May 21, 2020Date of Patent: October 18, 2022Assignee: HIMAX TECHNOLOGIES LIMITEDInventors: Yu-Jui Hsieh, Po-Nan Chen, Ya-Jing Yang
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Patent number: 11462264Abstract: Memory devices and methods are provided. In one aspect, a memory device may comprise a first field element, a second field element, a movable magnetic element, and a first heater. The first field element may be a superconductor. The second field element may be disposed facing the first field element and at a first distance from the first field element. The movable magnetic element may be repelled by the second field element and disposed in a space between the first field element and the second field element. The first heater may be arranged near the first field element. The movable magnetic element may move toward the first field element in response to a first electric current that passes through the first heater.Type: GrantFiled: April 15, 2020Date of Patent: October 4, 2022Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.Inventor: Dan Yu
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Patent number: 11444218Abstract: The present invention relates to a device for operating with THz and/or IR and/or MW radiation, comprising: —an antenna having one or more antenna branches (A1; A1, A2) and adapted to operate in the THz and/or IR and/or MW frequency range; and —a structure made of at least one photoactive material defining a photo-active area (Ga) arranged to absorb light radiation impinging thereon. The focus area of the at least one antenna branch (A1; A1, A2) is dimensionally equal or smaller than the photo-active area (Ga).Type: GrantFiled: December 24, 2018Date of Patent: September 13, 2022Assignees: FUNDACIÓ INSTITUT DE CIÈNCIES FOTÓNIQUES, INSTITUCIÓ CATALANA DE RECERCA I ESTUDIS AVANÇATS, ASOCIACIÓN CENTRO DE INVESTIGACIÓN COOPERATIVA EN NANOCIENCIAS, CIC NANOGUNEInventors: Klaas-Jan Tielrooij, Frank Koppens, Rainer Hillenbrand, Marta Autore
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Patent number: 11424375Abstract: A photoelectronic device includes a substrate; a first electrode and a second electrode disposed on the substrate and spaced apart from each other in a first direction; and a transition metal dichalcogenide thin film including at least one first region and at least one second region. Each first region includes M+N transition metal dichalcogenide molecular layers and extends along the first direction. Each second region includes N transition metal dichalcogenide molecular layers extending from lower N transition metal dichalcogenide molecular layers of the first region. Each second region extends along the first direction and is adjacent to each first region. Both end regions in the first direction among the first and the second regions are electrically connected to the first electrode and the second electrode, respectively.Type: GrantFiled: February 25, 2020Date of Patent: August 23, 2022Assignee: Research & Business Foundation Sungkyunkwan UniversityInventors: Geun Young Yeom, Ki Seok Kim, Ki Hyun Kim, You Jin Ji, Ji Young Byun
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Patent number: 11362232Abstract: A photodiode, such as a linear mode avalanche photodiode can be made free of excess noise via having a superlattice multiplication region that allows only one electrical current carrier type, such as an electron or a hole, to accumulate enough kinetic energy to impact ionize when biased, where the layers are lattice matched. A photodiode can be constructed with i) a lattice matched pair of a first semiconductor alloy and a second semiconductor alloy in a superlattice multiplication region, ii) an absorber region, and iii) a semiconductor substrate. A detector with multiple photodiodes can be made with these construction layers in order to have a cutoff wavelength varied anywhere from 1.7 to 4.9 ?m as well as a noise resulting from a dark current at a level such that an electromagnetic radiation signal with the desired minimum wavelength cutoff can be accurately sensed by the photodiode.Type: GrantFiled: May 24, 2019Date of Patent: June 14, 2022Assignee: SRI InternationalInventor: Winston K. Chan
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Patent number: 11362080Abstract: A semiconductor arrangement includes at least one switching device, electrically coupled between a first terminal and a second terminal, at least one diode, coupled in parallel to the at least one switching device between the first terminal and the second terminal, at least one bonding pad, and at least one electrically connecting element. Each of the at least one electrically connecting element is arranged to electrically couple one of the at least one switching device to one of the at least one diode. Each electrically connecting element includes a first end, a second end, and a middle section, and for at least one of the electrically connecting element, the first end is mechanically coupled to the respective switching device, the second end is mechanically coupled to the respective diode, and the middle section is mechanically coupled to at least one of the at least one bonding pad.Type: GrantFiled: November 27, 2019Date of Patent: June 14, 2022Inventors: Christian Robert Mueller, Christoph Urban
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Patent number: 11355684Abstract: An aspect of the invention provides a multilayer circuit substrate that has a simple configuration and is thin. The multilayer circuit substrate has a stacked multiple of substrates and a wiring pattern disposed so to be sandwiched between the stacked multiple of substrates. At least one portion of the wiring pattern is configured of a conductive material wherein conductive particles are sintered. An upper face of the wiring pattern is directly joined to the substrate positioned above the wiring pattern, a lower face of the wiring pattern is directly joined to the substrate positioned below the wiring pattern, and the stacked multiple of substrates are fixed to each other by the wiring pattern.Type: GrantFiled: May 1, 2019Date of Patent: June 7, 2022Assignee: STANLEY ELECTRIC CO., LTD.Inventor: Akihiko Hanya
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Patent number: 11309447Abstract: One illustrative photodiode disclosed herein includes an N-doped anode region, a P-doped cathode region and at least one P-doped charge region positioned laterally between the N-doped anode region and the P-doped cathode region. In this example, the photodiode also includes a plurality of quantum dots embedded within the at least one P-doped charge region and an N-doped impact ionization region positioned laterally between the N-doped anode region and the at least one P-doped charge region.Type: GrantFiled: December 26, 2019Date of Patent: April 19, 2022Assignee: GlobalFoundries U.S. Inc.Inventors: Ajey Poovannummoottil Jacob, Yusheng Bian
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Patent number: 11309463Abstract: A light emitting device includes a substrate, a LED element placed on the substrate, and a lens placed on an optical path of the LED element, wherein the lens has a convex part protruding in a direction of an optical axis of the lens in a central part of an exit surface of the lens.Type: GrantFiled: March 30, 2018Date of Patent: April 19, 2022Assignee: HOYA CORPORATIONInventor: Taiji Mizuta
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Patent number: 11305364Abstract: A solar cell connecting method for manufacturing a solar cell string, includes placing first interconnectors on a working table by a first fixing member fixing both sides of the first interconnectors in a longitudinal direction and transporting the first interconnectors in a state that the first interconnectors are spaced apart from each other at intervals; placing a first solar cell on the first interconnectors, fixing the first solar cell and the first interconnectors by an exhaust adsorption, and releasing the first fixing member from the first interconnectors; and placing second interconnectors on the first solar cell and the working table by the first fixing member fixing both sides of the second interconnectors in a longitudinal direction and transporting the second interconnectors in a state that the second interconnectors are spaced apart from each other at intervals.Type: GrantFiled: April 30, 2019Date of Patent: April 19, 2022Assignee: LG ELECTRONICS INC.Inventors: Sunghyun Hwang, Jinsung Kim, Woojoong Kang, Jangho Kim, Dongju Kang, Kyuhyeok Sim
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Patent number: 11296255Abstract: A method of manufacturing a light-emitting element including, in the following order, steps of: preparing a wafer on which a semiconductor layer including an light-emission layer is formed; forming a resist film comprising a main body and a protrusion; forming a first metal film; forming a second metal film on the resist film and on the first metal film; pulling the protrusion of the resist film upward by raising and then lowering a temperature of the wafer; forming a third metal film on the second metal film and covering an end of the first metal film by the third metal film; and removing the resist film. In the step of forming the second metal film, the end of the first metal film is exposed from the second metal film.Type: GrantFiled: January 24, 2020Date of Patent: April 5, 2022Assignee: NICHIA CORPORATIONInventors: Kosuke Sato, Kazuya Nakao
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Patent number: 11295770Abstract: A thin-film piezoelectric material substrate includes an insulator on Si substrate and a thin-film laminated part. The insulator on Si substrate has a substrate for deposition made of silicon and an insulating layer formed on a surface of the substrate for deposition. The thin-film laminated part is formed on a top surface of the insulating layer. The thin-film laminated part has a YZ seed layer including yttrium and zirconium, and formed on the top surface; a lower electrode film laminated on the YZ seed layer; a piezoelectric material film made of lead zirconate titanate, shown by general formula Pb(ZrxTi(1-x))O3, and formed on the lower electrode film; and an upper electrode film laminated on the piezoelectric material film.Type: GrantFiled: March 1, 2019Date of Patent: April 5, 2022Assignee: SAE MAGNETICS (H.K.) LTD.Inventors: Wei Xiong, Atsushi Iijima
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Patent number: 11289568Abstract: The present disclosure relates to a MIM (metal-insulator-metal) capacitor having a top electrode overlying a substrate. A passivation layer overlies the top electrode. The passivation layer has a step region that continuously contacts and extends from a top surface of the top electrode to sidewalls of the top electrode. A metal frame overlies the passivation layer. The metal frame continuously contacts and extends from a top surface of the passivation layer to upper sidewalls of the passivation layer in the step region. The metal frame has a protrusion that extends through the passivation layer and contacts the top surface of the top electrode.Type: GrantFiled: May 13, 2019Date of Patent: March 29, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Yuan Shih, Kai-Fung Chang, Shih-Fen Huang, Wen-Chuan Tai, Yi-Chuan Teng, Yi Heng Tsai, You-Ru Lin, Yen-Wen Chen, Anderson Lin, Fu-Chun Huang, Chun-Ren Cheng, Ivan Hua-Shu Wu, Fan Hu, Ching-Hui Lin, Yan-Jie Liao
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Patent number: 11282860Abstract: The semiconductor device includes a first layer including a first transistor, a second layer including a first insulating film over the first layer, a third layer including a second insulating film over the second layer, and a fourth layer including a second transistor over the third layer. A first conductive film electrically connects the first transistor and the second transistor to each other through an opening provided in the first insulating film. A second conductive film electrically connects the first transistor, the second transistor, and the first conductive film to one another through an opening provided in the second insulating film. A channel formation region of the first transistor includes a single crystal semiconductor. A channel formation region of the second transistor includes an oxide semiconductor. The width of a bottom surface of the second conductive film is 5 nm or less.Type: GrantFiled: May 18, 2020Date of Patent: March 22, 2022Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Motomu Kurata, Shinya Sasagawa, Ryota Hodo, Katsuaki Tochibayashi, Tomoaki Moriwaka, Jiro Nishida, Hidekazu Miyairi, Shunpei Yamazaki
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Patent number: 11264466Abstract: A semiconductor device includes a semiconductor layer including a Ga2O3-based single crystal, and an electrode that is in contact with a surface of the semiconductor layer. The semiconductor layer is in Schottky-contact with the electrode and has an electron carrier concentration based on reverse withstand voltage and electric field-breakdown strength of the Ga2O3-based single crystal.Type: GrantFiled: February 26, 2020Date of Patent: March 1, 2022Assignee: TAMURA CORPORATIONInventors: Masaru Takizawa, Akito Kuramata
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Patent number: 11264292Abstract: Various embodiments of the present application are directed to an integrated circuit (IC) comprising a floating gate test device with a cell-like top layout, as well as a method for forming the IC. In some embodiments, the IC comprises a semiconductor substrate and the floating gate test device. The floating gate test device is on the semiconductor substrate, and comprises a floating gate electrode and a control gate electrode overlying the floating gate electrode. The floating gate electrode and the control gate electrode partially define an array of islands, and further partially define a plurality of bridges interconnecting the islands. The islands and the bridges define the cell-like top layout and may, for example, prevent process-induced damage to the floating gate test device.Type: GrantFiled: November 13, 2019Date of Patent: March 1, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Meng-Han Lin, Chih-Ren Hsieh, Ya-Chen Kao, Chen-Chin Liu, Chih-Pin Huang