Patents Examined by Howard Weiss
  • Patent number: 9373655
    Abstract: An imaging device includes: a photoelectric conversion region that generates photovoltaic power for each pixel depending on irradiation light; and a first element isolation region that is provided between adjacent photoelectric conversion regions in a state of surrounding the photoelectric conversion region.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: June 21, 2016
    Assignee: Sony Corporation
    Inventors: Tsutomu Imoto, Keiji Mabuchi
  • Patent number: 9368492
    Abstract: A semiconductor substrate may be formed by providing an providing a semiconductor-on-insulator (SOI) substrate including a base semiconductor layer, a buried insulator layer above the base semiconductor layer, and a SOI layer comprising a first semiconductor material above the buried insulator layer; forming an isolation region in the SOI layer isolating a first portion of the SOI layer from a second portion of the SOI layer; removing the second portion of the SOI layer to expose a portion of the buried insulator layer; forming a hole in the exposed portion of the buried insulator layer to expose a portion of the base semiconductor layer; and forming a semiconductor layer made of a second semiconductor material on the exposed portion of the base semiconductor layer, so that the replacement semiconductor layer covers the exposed region of the buried insulator layer.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: June 14, 2016
    Assignee: GLOBALFOUNDRIES
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 9365412
    Abstract: A monolithically integrated CMOS and MEMS device. The device includes a first semiconductor substrate having a first surface region and one or more CMOS IC devices on a CMOS IC device region overlying the first surface region. The CMOS IC device region can also have a CMOS surface region. A bonding material can be provided overlying the CMOS surface region to form an interface by which a second semiconductor substrate can be joined to the CMOS surface region. The second semiconductor substrate has a second surface region coupled to the CMOS surface region by bonding the second surface region to the bonding material. The second semiconductor substrate includes one or more first air dielectric regions. One or more free standing MEMS structures can be formed within one or more portions of the processed first substrate.
    Type: Grant
    Filed: April 3, 2013
    Date of Patent: June 14, 2016
    Assignee: mCube Inc.
    Inventor: Xiao (Charles) Yang
  • Patent number: 9356144
    Abstract: The present disclosure relates to gate oxide protection circuits, which are used to protect the gate oxides of field effect transistor (FET) elements from over voltage conditions, particularly during situations in which the gate oxides are particularly vulnerable, such as during certain manufacturing stages. Each gate oxide protection circuit may be coupled to a corresponding FET element through corresponding first and second resistive elements, which are coupled to a corresponding gate connection node and a corresponding first connection node, respectively, of the FET element. The gate connection node and the first connection node are electrically adjacent to opposite sides of the gate oxide of the FET element. Each gate oxide protection circuit may protect its corresponding FET element by limiting a voltage between the gate connection node and the first connection node.
    Type: Grant
    Filed: August 11, 2010
    Date of Patent: May 31, 2016
    Assignee: RF Micro Devices, Inc.
    Inventors: Philip Mason, Daniel Charles Kerr, Michael Carroll
  • Patent number: 9356097
    Abstract: Embodiments of the present invention include a method for forming a semiconductor emitter and the resulting structure. The invention comprises forming an epitaxial base layer on a semiconductor substrate. A dielectric layer is deposited over the epitaxial base layer. An opening is etched in a portion of the dielectric layer exposing a portion of the epitaxial base layer and a spacer is deposited along the sidewall of the opening. The emitter is grown from the epitaxial base layer to overlap the top surface of the spacer and a portion of the dielectric layer. The single crystal emitter is formed without a mask and without the requirement of subsequent patterning processes.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: May 31, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: David L. Harame, Vikas K. Kaushal, Marwan H. Khater, Qizhi Liu
  • Patent number: 9356063
    Abstract: Provided is an image sensor including a photoelectric conversion unit for converting a received light into an electric charge; a semiconductor substrate including the photoelectric conversion unit; and a plurality of areas each having a refractive index different from a refractive index of the semiconductor substrate formed between a surface of the semiconductor substrate on which light is incident and the photoelectric conversion unit. Also, provided are an apparatus and a method of producing the image sensor, and an electronic device including the image sensor.
    Type: Grant
    Filed: July 3, 2014
    Date of Patent: May 31, 2016
    Assignee: Sony Corporation
    Inventor: Harumi Ikeda
  • Patent number: 9355904
    Abstract: A semiconductor die including strain relief for through substrate vias (TSVs). A method for strain relief of TSVs includes defining a through substrate via cavity in a substrate. The method also includes depositing an isolation layer in the cavity. The method further includes filling the cavity with a conductive material. The method also includes removing a portion of the isolation layer to create a recessed portion.
    Type: Grant
    Filed: June 23, 2014
    Date of Patent: May 31, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Vidhya Ramachandran, Shiqun Gu
  • Patent number: 9349772
    Abstract: A method of fabricating an integrated circuit includes depositing a bottom electrode layer, an MTJ layer, and a top electrode layer over a passivation layer and within a trench of the passivation layer and removing portions of the MTJ layer and the top electrode layer to form an MTJ/top electrode stack over the bottom electrode layer and at least partially within portions of the trench having being reopened by said removing. The method further includes forming a further passivation layer over the MTJ/top electrode stack, forming a further ILD layer of the further passivation layer, and reforming a top electrode layer over the ILD layer and over the MTJ/top electrode stack. Still further, the method includes removing portions of the bottom electrode layer, the further passivation layer, the further ILD layer, and the re-formed top electrode layer to form a bottom electrode/MTJ/top electrode stack.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: May 24, 2016
    Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.
    Inventors: Wanbing Yi, Yang Hong, Yi Jiang, Francis Poh, Tze Ho Simon Chan, Juan Boon Tan
  • Patent number: 9343526
    Abstract: An integrated semiconductor device includes a substrate of a first conductivity type, a buried layer located over the substrate, an isolated region located over a first portion of the buried layer, and an isolation trench located around the isolated region. A punch-through structure is located around at least a portion of the isolation trench. The punch-through structure includes a second portion of the buried layer, a first region located over the second portion of the buried layer, the first region having a second conductivity type, and a second region located over the first region, the second region having the first conductivity type.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 17, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Xu Cheng, Daniel J. Blomberg, Zhihong Zhang, Jiang-Kai Zuo
  • Patent number: 9344092
    Abstract: A technique relates to a superconductor tunable notch filter. A Josephson junction filter array is connected to a coupling pad and connected to ground. The Josephson junction filter array includes a filter inductance. The Josephson junction filter array connected to the coupling pad forms a filter capacitance. A Josephson junction bias array is connected to the coupling pad and connected to a current source. The Josephson junction bias array includes a bias inductance. A transmission line is connected to the coupling pad in which connection of the transmission line and the coupling pad forms a coupling capacitance, such that the filter inductance and the filter capacitance connect to the transmission line through the coupling capacitance. The Josephson junction filter array includes a notch filter frequency that is tunable according to a magnitude of a current bias from the current source.
    Type: Grant
    Filed: August 7, 2014
    Date of Patent: May 17, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: David W. Abraham, Jerry M. Chow, Jay M. Gambetta, Nicholas A. Masluk, Matthias Steffen
  • Patent number: 9343607
    Abstract: A novel photo-sensitive element for electronic imaging purposes and, in this context, is particularly suited for time-of-flight 3D imaging sensor pixels. The element enables charge-domain photo-detection and processing based on a single gate architecture. Certain regions for n and p-doping implants of the gates are defined. This kind of single gate architecture enables low noise photon detection and high-speed charge transport methods at the same time. A strong benefit compared to known pixel structures is that no special processing steps are required such as overlapping gate structures or very high-ohmic poly-silicon deposition. In this sense, the element relaxes the processing methods so that this device may be integrated by the use of standard CMOS technology for example. Regarding time-of-flight pixel technology, a major challenge is the generation of lateral electric fields. The element allows the generation of fringing fields and large lateral electric fields.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: May 17, 2016
    Assignee: Heptagon Micro Optics Pte. Ltd.
    Inventors: Bernhard Buettgen, Michael Lehmann, Miguel Bruno Vaello PaƱos
  • Patent number: 9343658
    Abstract: A basic Spin-Orbit-Torque (SOT) structure with lateral structural asymmetry is provided that produces a new spin-orbit torque, resulting in zero-field current-induced switching of perpendicular magnetization. More complex structures can also be produced incorporating the basic structure of a ferromagnetic layer with a heavy non-magnetic metal layer having strong spin-orbit coupling on one side, and an insulator layer on the other side with a structural mirror asymmetry along the in-plane direction. The lateral structural asymmetry and new spin-orbit torque, in effect, replaces the role of the external in-plane magnetic field. The direction of switching is determined by the combination of the direction of applied current and the direction of symmetry breaking in the device.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: May 17, 2016
    Assignee: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA
    Inventors: Kang L. Wang, Pedram Khalili Amiri, Guoqiang Yu, Pramey Upadhyaya
  • Patent number: 9337109
    Abstract: A multi-threshold voltage (Vt) field-effect transistor (FET) formed through strain engineering is provided. An embodiment integrated circuit device includes a first transistor including a first channel region over a first buffer, the first channel region formed from a III-V semiconductor material and a second transistor including a second channel region over a second buffer, the second channel region formed from the III-V semiconductor material, the second buffer and the first buffer having a lattice mismatch. A first strain introduced by a lattice mismatch between the III-V semiconductor material and the first buffer is different than a second strain introduced by a lattice mismatch between the III-V semiconductor material and the second buffer. Therefore, the threshold voltage of the first transistor is different than the threshold voltage of the second transistor.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: May 10, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Gerben Doornbos, Krishna Kumar Bhuwalka
  • Patent number: 9324675
    Abstract: A semiconductor structure includes a bond pad and a wire bond coupled to the bond pad. The wire bond includes a bond in contact with the bond pad. The wire bond includes a coating on a surface of the wire bond, and a first exposed portion of the wire bond in a selected location. The wire bond is devoid of the coating over the selected location of the wire bond, and an area of the first exposed portion is at least one square micron.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: April 26, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Burton J. Carpenter, Chu-Chung Lee, Tu-Anh N. Tran
  • Patent number: 9324814
    Abstract: A silicon carbide single-crystal substrate includes a first surface, a second surface opposite to the first surface, and a peripheral edge portion sandwiched between the first surface and the second surface. A plurality of grinding traces are formed in a surface of the peripheral edge portion. A chamfer width as a distance from an outermost peripheral end portion of the peripheral edge portion to one of the plurality of grinding traces which is located on an innermost peripheral side of the peripheral edge portion in a direction parallel to the first surface is not less than 50 ?m and not more than 400 ?m. Thereby, a silicon carbide single-crystal substrate capable of suppressing occurrence of a crack, and a method for manufacturing the same can be provided.
    Type: Grant
    Filed: February 10, 2015
    Date of Patent: April 26, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kyoko Okita, Keiji Ishibashi
  • Patent number: 9324673
    Abstract: A method of manufacture of an integrated circuit packaging system includes: removing a portion of a leadframe to form a partially removed region and an upper portion of a peripheral lead on the leadframe first side; mounting a first integrated circuit over the partially removed region with a first adhesive; forming a first molding layer directly on the first integrated circuit and the peripheral lead; removing a portion of a leadframe second side exposing the first adhesive; mounting a second integrated circuit on the first adhesive of the first integrated circuit; forming a first interconnection layer directly on the first integrated circuit with the first integrated circuit and the peripheral lead electrically connected; and forming a second interconnection layer directly on the second integrated circuit with the second integrated circuit and the peripheral lead electrically connected.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: April 26, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventor: Zigmund Ramirez Camacho
  • Patent number: 9318477
    Abstract: A semiconductor device is disclosed. The semiconductor device includes a plurality of dummy gate lines parallel to each other in a first direction and extending in a second direction that is orthogonal to the first direction; a plurality of first dummy filling patterns between the plurality of dummy gate lines, the first dummy filling patterns parallel to each other in the first direction, and arranged apart from each other in the second direction; a plurality of first dummy vias on the plurality of first dummy filling patterns; and a plurality of first dummy wiring lines connected to the plurality of first dummy vias, the first dummy vias extending in the second direction, and parallel to each other in the first direction.
    Type: Grant
    Filed: September 23, 2014
    Date of Patent: April 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-myoung Lee, Young-soo Song, Bo-young Lee, Jun-min Lee
  • Patent number: 9318563
    Abstract: A silicon carbide single-crystal substrate includes a first surface, a second surface opposite to the first surface, and a peripheral edge portion sandwiched between the first surface and the second surface. A plurality of grinding traces are formed in a surface of the peripheral edge portion. A chamfer width as a distance from an outermost peripheral end portion of the peripheral edge portion to one of the plurality of grinding traces which is located on an innermost peripheral side of the peripheral edge portion in a direction parallel to the first surface is not less than 50 ?m and not more than 400 ?m. Thereby, a silicon carbide single-crystal substrate capable of suppressing occurrence of a crack, and a method for manufacturing the same can be provided.
    Type: Grant
    Filed: February 11, 2015
    Date of Patent: April 19, 2016
    Assignee: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Kyoko Okita, Keiji Ishibashi
  • Patent number: 9318464
    Abstract: Various methods of mounting semiconductor chips on a substrate are disclosed. In one aspect, a method of manufacturing is provided that includes coupling a first plurality of solder interconnect structures to a first semiconductor chip. The first solder interconnect structures have a first melting point. The first semiconductor chip may be tested. If the first semiconductor chip passes the testing, then a second semiconductor chip is coupled to the first semiconductor chip using a second plurality of solder interconnect structures that have a second melting point lower than the first melting point.
    Type: Grant
    Filed: May 21, 2013
    Date of Patent: April 19, 2016
    Assignee: Advanced Micro Devices, Inc.
    Inventor: David H. Eppes
  • Patent number: 9312336
    Abstract: A semiconductor device includes a drain region, an epitaxial layer overlaying the drain region, and an active region. The active region includes: a body disposed in the epitaxial layer; a source embedded in the body; a gate trench extending into the epitaxial layer; a gate disposed in the gate trench; a contact trench extending through the source and at least part of the body; a contact electrode disposed in the contact trench; and an implant disposed at least in part along a contact trench wall; and an epitaxial enhancement portion disposed below the contact trench and in contact with the implant.
    Type: Grant
    Filed: October 18, 2013
    Date of Patent: April 12, 2016
    Assignee: Alpha and Omega Semiconductor Incorporated
    Inventors: Ji Pan, Anup Bhalla