Abstract: A process of overlay offset measurement includes providing a substrate; forming a first pattern layer with a predetermined first pattern on the substrate; forming a first photoresist layer on the substrate and the first pattern layer; forming a second photoresist layer on the first photoresist layer; forming a second pattern layer with a predetermined second pattern on the second photoresist layer; patterning the second photoresist layer to form a trench having a predetermined third pattern being substantially aligned with the predetermined first pattern of the first pattern layer; and performing overlay offset measurement according to the second pattern layer and the trench.

Abstract: A leadframe includes leads or lead terminals, a plurality of folded features including i) support features positioned within an area defined in at least one dimension by the leads or the lead terminals configured for supporting at least one of a die pad and a first pad and a second pad spaced apart from one another, or ii) current carrying features. At least one of the folded features includes a planar portion and a folded edge structure that curves upwards at an angle of at least 45° relative to the planar portion. The folded features are configured to provide an effective increase in thickness to reduce the deformation observed in assembly.

Abstract: In a described example, a method for forming a capacitor includes: forming a capacitor first plate over a non-conductive substrate; flowing ammonia and nitrogen gas into a plasma enhanced chemical vapor deposition (PECVD) chamber containing the non-conductive substrate; stabilizing a pressure and a temperature in the PECVD chamber; turning on radio frequency high frequency (RF-HF) power to the PECVD chamber; pretreating the capacitor first plate for at least 60 seconds; depositing a capacitor dielectric on the capacitor first plate; and depositing a capacitor second plate on the capacitor dielectric.

Abstract: A semiconductor structure includes a multilayer structure having a first layer and a second layer disposed on the first layer. The semiconductor structure further includes at least a first via extending from a top of the second layer to a top of a first metal contact disposed in the first layer. A polymer film is disposed on at least a portion of sidewalls of the first via.

Abstract: Various implementations described herein refer to a device having logic circuitry with transistors and gate lines. The device may include a backside power network having buried supply rails with at least one buried supply rail having a continuity break. The transistors may be arranged in a cell architecture having an N-well break with the gate lines passing through the N-well break and the continuity break.

Abstract: A MEMS transducer for interacting with a volume flow of a fluid includes a substrate which includes a layer stack having a plurality of layers which form a plurality of substrate planes, and which includes a cavity within the layer stack. The MEMS transducer includes an electromechanical transducer connected to the substrate within the cavity and including an element which is deformable within at least one plane of movement of the plurality of substrate planes, deformation of the deformable element within the plane of movement and the volume flow of the fluid being causally correlated. The MEMS transducer includes an electronic circuit arranged within a layer of the layer stack, the electronic circuit being connected to the electromechanical transducer and being configured to provide a conversion between a deformation of the deformable element and an electric signal.

Abstract: A method includes fusion bonding a handle wafer to a first side of a device wafer. The method further includes depositing a first mask on a second side of the device wafer, wherein the second side is planar. A plurality of dimple features is formed on an exposed portion on the second side of the device wafer. The first mask is removed from the second side of the device wafer. A second mask is deposited on the second side of the device wafer that corresponds to a standoff. An exposed portion on the second side of the device wafer is etched to form the standoff. The second mask is removed. A rough polysilicon layer is deposited on the second side of the device wafer. A eutectic bond layer is deposited on the standoff. In some embodiments, a micro-electro-mechanical system (MEMS) device pattern is etched into the device wafer.

Abstract: The present technology relates to a solid-state imaging device, a manufacturing method, and an electronic device, which can improve sensitivity while improving color mixing. The solid-state imaging device includes a first wall provided between a pixel and a pixel arranged two-dimensionally to isolate the pixels, in which the first wall includes at least two layers including a light shielding film of a lowermost layer and a low refractive index film of which refractive index is lower than the light shielding film. The present technology can be applied to, for example, a solid-state imaging device, an electronic device having an imaging function, and the like.

Abstract: An electronic device includes: a base substrate including an active region, which includes a sensing region, and a peripheral region adjacent to the active region; an input sensor including a sensing insulating layer, a plurality of first sensing electrodes, a plurality of second sensing electrodes, the second sensing electrodes being spaced apart from the first sensing electrodes; and a pressure sensor including a plurality of strain sensing patterns overlapping the sensing region, and strain connection patterns connecting the strain sensing patterns to each other, wherein each of the first sensing electrodes comprises a plurality of first sensing patterns overlapping the active region, each of the second sensing electrodes comprises a plurality of second sensing patterns overlapping the active region and on a same layer as the first sensing patterns, and a plurality of second connection patterns connecting the second sensing patterns.

Abstract: A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.

Abstract: Some embodiments include an integrated assembly. The integrated assembly includes active regions which each have a digit-line-contact-region between a pair of capacitor-contact-regions. The capacitor-contact-regions are arranged in a pattern such that six adjacent capacitor-contact-regions form a substantially rectangular configuration. Conductive redistribution material is coupled with the capacitor-contact-regions and extends upwardly and laterally outwardly from the capacitor-contact-regions. Upper surfaces of the conductive redistribution material are arranged in a pattern such that seven adjacent of the upper surfaces form a unit of a substantially hexagonal-close-packed configuration. Capacitors are coupled with the upper surfaces of the conductive redistribution material.

Abstract: A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

Abstract: An organic electroluminescent element includes, in order, a first electrode, an organic light-emitting layer, a buffer layer, a metal thin film, an organic electron transport layer, and a second electrode. The buffer layer includes an electrically-conductive organic material. The metal thin film includes a metal or a metal alloy. The organic electron transport layer is doped with a metal. The metal in the metal thin film is the same as the metal doped in the organic electron transport layer. The metal alloy in the metal thin film includes a metal that is the same as the metal doped in the organic electron transport layer.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate, wherein the substrate comprises a first semiconductor layer, an insulating layer, and a second semiconductor layer; forming an active device on the substrate; forming an interlayer dielectric (ILD) layer on the substrate and the active device; forming a first contact plug in the ILD layer to electrically connect the active device; and forming a second contact plug in the ILD layer and the insulating layer after forming the first contact plug.

Abstract: A semiconductor package includes a leadframe, a semiconductor die attached to the leadframe, and a passive component electrically connected to the semiconductor die through the leadframe. The leadframe includes a cavity in a side of the leadframe opposite the semiconductor die, and at least a portion of the passive component resides within the cavity in a stacked arrangement.

Abstract: A semiconductor structure and a method of fabricating the same are disclosed. The semiconductor structure comprises an active region over a substrate defining a top surface and a gate structure embedded in the active region. In a cross section of the active region, the gate structure includes a conductive feature having a first width buried in the active region and reaching a first depth therein; an insulating cap having a second width arranged above the conductive feature in the active region and reaching a second depth therein; and a dielectric liner arranged between the active region and the conductive feature. The first width is smaller than the second width.

Abstract: A packaged electrical device that includes a cured adhesive layer and a cured layer of die attach material coupled between a semiconductor die and a substrate. The packaged electrical device may also include wire bonds coupled between the substrate and leads of the semiconductor die. In addition, the packaged electrical device may be encapsulated in molding compound. A method for fabricating a packaged electrical device. The method includes printing a layer of die attach material over a semiconductor wafer and applying a layer of 2-in-1 die attach film over the layer of die attach material. The method also includes singulating the semiconductor wafer to create a semiconductor die and placing the semiconductor die onto a substrate. In addition the method includes wire bonding the substrate to leads of the semiconductor die and encapsulating the device in molding compound.

Abstract: An apparatus is provided which comprises: a first stack comprising a magnetic insulating material (MI such as, EuS, EuO, YIG, TmIG, or GaMnAs) and a transition metal dichalcogenide (TMD such as MoS2, MoSe2, WS2, WSe2, PtS2, PtSe2, WTe2, MoTe2, or graphene; a second stack comprising an MI material and a TMD, wherein the first and second stacks are separated by an insulating material (e.g., oxide); a magnet (e.g., a ferromagnet or a paramagnet) adjacent to the TMDs of the first and second stacks, and also adjacent to the insulating material; and a magnetoelectric material (e.g., (LaBi)FeO3, LuFeO3, PMN-PT, PZT, AlN, or (SmBi)FeO3) adjacent to the magnet.

Abstract: A heterogeneous semiconductor structure, including a first integrated circuit and a second integrated circuit, the second integrated circuit being a photonic integrated circuit. The heterogeneous semiconductor structure may be fabricated by bonding a multi-layer source die, in a flip-chip manner, to the first integrated circuit, removing the substrate of the source die, and fabricating one or more components on the source die, using etch and/or deposition processes, to form the second integrated circuit. The second integrated circuit may include components fabricated from cubic phase gallium nitride compounds, and configured to operate at wavelengths shorter than 450 nm.

Abstract: An image sensor includes a plurality of pixels each including: a first and a second photoelectric conversion unit that perform photoelectric conversion upon light that has passed through a micro lens and generates a charge; a first accumulation unit that accumulates the charge generated by the first conversion unit; a second accumulation unit that accumulates the charge generated by the second conversion unit; a third accumulation unit that accumulates the charges generated by the first and second conversion units; a first transfer unit that transfers the charge generated by the first conversion unit to the first accumulation unit; a second transfer unit that transfers the charge generated by the second conversion unit to the second accumulation unit; and a third transfer unit that transfers the charges generated by the first and second conversion units to the third accumulation unit.