Patents Examined by Hung Vu
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Patent number: 9985108Abstract: An electrode comes in ohmic contact with an AlGaN layer. A semiconductor device SD has a nitride semiconductor layer GN2, and an AlxGa(1-x)N layer AGN (hereinafter referred to as “AlGaN layer AGN), and Al electrodes DE, SE. in the AlGaN layer AGN, 0<x?0.2 is satisfied. Also, both of a concentration of a p-type impurity and a concentration of an n-type impurity in the AlGaN layer AGN are 1×1016 cm?3 or lower. In this example, the p-type impurity is exemplified by, for example, Be, C, and Mg, and the n-type impurity is exemplified by Si, S, and Se. Also, the Al electrodes DE and SE are connected to the AlGaN layer AGN. Because a composition ratio of Al is limited to the above-mentioned range, the Al electrodes DE and SE are brought into ohmic contact with the AlGaN layer AGN.Type: GrantFiled: July 14, 2014Date of Patent: May 29, 2018Assignee: RENESAS ELECTRONICS CORPORATIONInventors: Tatsuo Nakayama, Masaaki Kanazawa, Yasuhiro Okamoto, Takashi Inoue, Hironobu Miyamoto, Ryohei Nega
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Patent number: 9984962Abstract: Systems and methods for flexible hybrid electronic (FHE) systems integrate traditional rigid integrated circuits with flexible substrates and/or interconnects. The layout and components of the system may be selected and/or optimized for a desired level of performance or flexibility. Via use of exemplary FHE system principles, improved wearable devices and other portable electronic systems may be realized.Type: GrantFiled: August 30, 2016Date of Patent: May 29, 2018Assignee: Arizona Board of Regents on behalf of Arizona State UniversityInventors: Umit Y. Ogras, Ujjwal Gupta, Md Ali Muztoba
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Patent number: 9984938Abstract: A method includes providing a substrate having a first gate region for a first device and a second gate region for a second device, the first and second gate regions having different channel lengths. The method further includes forming first and second fins in at least the first and second gate regions respectively, and forming first and second stacks of semiconductor layers over the first and second fins respectively. The method further includes performing an oxidation process to the first and second stacks, thereby forming first and second semiconductor wires in the first and second gate regions respectively. Each of the first and second semiconductor wires is wrapped by a semiconductor oxide layer. The first and second semiconductor wires have different cross-sectional geometries in a respective plane that is perpendicular to their respective longitudinal direction.Type: GrantFiled: May 26, 2016Date of Patent: May 29, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kuo-Cheng Ching, Jiun-Jia Huang
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Patent number: 9985069Abstract: An object is to achieve low-power consumption by reducing the off-state current of a transistor in a photosensor. A semiconductor device including a photosensor having a photodiode, a first transistor, and a second transistor; and a read control circuit including a read control transistor, in which the photodiode has a function of supplying charge based on incident light to a gate of the first transistor; the first transistor has a function of storing charge supplied to its gate and converting the charge stored into an output signal; the second transistor has a function of controlling reading of the output signal; the read control transistor functions as a resistor converting the output signal into a voltage signal; and semiconductor layers of the first transistor, the second transistor, and the read control transistor are formed using an oxide semiconductor.Type: GrantFiled: June 16, 2015Date of Patent: May 29, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Yoshiyuki Kurokawa, Takayuki Ikeda, Hikaru Tamura, Munehiro Kozuma
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Patent number: 9978914Abstract: A light emitting device includes a board, a light emitting element, a phosphor layer and a cover layer. The light emitting element is mounted on the board. The phosphor layer is in a substantially uniform thickness composed of a plurality of layers formed on a surface of the light emitting element. The cover layer contains light reflecting material at a place on the board where the light emitting element is not mounted. The cover layer covers the phosphor layer.Type: GrantFiled: May 9, 2016Date of Patent: May 22, 2018Assignee: NICHIA CORPORATIONInventor: Suguru Beppu
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Patent number: 9978691Abstract: A device (e.g., a Doherty amplifier) housed in an air cavity package includes one or more isolation structures over a surface of a substrate and defining an active circuit area. The device also includes first and second adjacent circuits within the active circuit area, first and second leads coupled to the isolation structure(s) between opposite sides of the package and electrically coupled to the first circuit, third and fourth leads coupled to the isolation structure(s) between the opposite sides of the package and electrically coupled to the second circuit, a first terminal over the first side of the package between the first lead and the third lead, a second terminal over the second side of the package between the second lead and the fourth lead, and an electronic component coupled to the package and electrically coupled to the first terminal, the second terminal, or both the first and second terminals.Type: GrantFiled: January 14, 2016Date of Patent: May 22, 2018Assignee: NXP USA, INC.Inventors: Shun Meen Kuo, Paul R. Hart, Margaret A. Szymanowski
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Patent number: 9978799Abstract: There is provided a solid-state image sensor including a semiconductor substrate in which a plurality of pixels are arranged, and a wiring layer stacked on the semiconductor substrate and formed in such a manner that a plurality of conductor layers having a plurality of wirings are buried in an insulation film. In the wiring layer, wirings connected to the pixels are formed of two conductor layers.Type: GrantFiled: June 1, 2016Date of Patent: May 22, 2018Assignee: Sony CorporationInventor: Toshifumi Wakano
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Patent number: 9972730Abstract: A sensor device includes a first substrate of semiconductor material having opposing first and second surfaces, photodetectors configured to receive light impinging on the first surface, and first contact pads each exposed at both the first and second surfaces and electrically coupled to at least one of the photodetectors. A second substrate comprises opposing first and second surfaces, electrical circuits, a second contact pads each disposed at the first surface of the second substrate and electrically coupled to at least one of the electrical circuits, and a plurality of cooling channels formed as first trenches extending into the second surface of the second substrate but not reaching the first surface of the second substrate. The first substrate second surface is mounted to the second substrate first surface such that each of the first contact pads is electrically coupled to at least one of the second contact pads.Type: GrantFiled: October 11, 2016Date of Patent: May 15, 2018Assignee: Optiz, Inc.Inventors: Vage Oganesian, Zhenhua Lu
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Patent number: 9960185Abstract: A base and a manufacturing method thereof and a display device are provided, so that a problem of faultage of an insulating layer when forming the insulating layer on an aluminum electrode of a substrate is solved. The base includes an aluminum electrode in a first setting pattern on a substrate, and an aluminum oxide layer or an aluminum nitride layer (3) in a second setting pattern provided in a same layer with the aluminum electrode. The first setting pattern and the second setting pattern are complementary to each other.Type: GrantFiled: September 30, 2014Date of Patent: May 1, 2018Assignee: BOE Technology Group Co., Ltd.Inventors: Xiangyong Kong, Fengjuan Liu
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Patent number: 9960079Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.Type: GrantFiled: May 17, 2013Date of Patent: May 1, 2018Assignee: Intel CorporationInventors: Todd B. Myers, Nicholas R. Watts, Eric C. Palmer, Jui Min Lim
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Patent number: 9954036Abstract: A display device includes plural unit areas each of which includes low definition pixels as sub-pixels larger than a specified standard and high definition pixels as sub-pixels smaller than the specified standard and which are regularly arranged. The low definition pixels include a blue pixel and a red pixel, and the high definition pixels include a white pixel and a green pixel.Type: GrantFiled: October 26, 2015Date of Patent: April 24, 2018Assignee: Japan Display Inc.Inventor: Toshihiro Sato
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Patent number: 9953864Abstract: Semiconductor structures include a patterned interlayer dielectric overlaying a semiconductor substrate. The interlayer dielectric includes a first dielectric layer and at least one additional dielectric layer disposed on the first dielectric layer, wherein the patterned interlayer dielectric comprises at least one opening extending through the interlayer dielectric to the semiconductor substrate. Chemically enriched regions including ions of Si, P, B, N, O and combinations thereof are disposed in surfaces of the first dielectric layer and the at least one dielectric layer defined by the at least one opening. Also described are methods of for forming an interconnect structure in a semiconductor structure.Type: GrantFiled: August 30, 2016Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Lawrence A. Clevenger, Roger A. Quon, Terry A. Spooner, Wei Wang, Chih-Chao Yang
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Patent number: 9954022Abstract: The present disclosure relates to a CMOS image sensor having a doped region, arranged between deep trench isolation structures and an image sensing element, and an associated method of formation. In some embodiments, the CMOS image sensor has a pixel region disposed within a semiconductor substrate. The pixel region has an image sensing element configured to convert radiation into an electric signal. A plurality of back-side deep trench isolation (BDTI) structures extend into the semiconductor substrate on opposing sides of the pixel region. A doped region is laterally arranged between the BDTI structures and separates the image sensing element from the BDTI structures and the back-side of the semiconductor substrate. Separating the image sensing element from the BDTI structures prevents the image sensing element from interacting with interface defects near edges of the BDTI structures, and thereby reduces dark current and white pixel number.Type: GrantFiled: October 27, 2015Date of Patent: April 24, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Yuan Chen, Ching-Chun Wang, Dun-Nian Yaung, Hsiao-Hui Tseng, Jhy-Jyi Sze, Shyh-Fann Ting, Tzu-Jui Wang, Yen-Ting Chiang, Yu-Jen Wang, Yuichiro Yamashita
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Patent number: 9953269Abstract: A technique relates to an assembly for a quantum computing device. A quantum bus plane includes a first set of recesses. A readout plane includes a second set of recesses. A block is positioned to hold the readout plane opposite the quantum bus plane, such that the first set of recesses opposes the second set of recesses. A plurality of qubit chips are included where each has a first end positioned in the first set of recesses and has a second end positioned in the second set of recesses.Type: GrantFiled: June 7, 2016Date of Patent: April 24, 2018Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jerry M. Chow, Jay M. Gambetta, Mary B. Rothwell, James R. Rozen
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Patent number: 9947738Abstract: A display panel including: a substrate; a multi-layer wiring layer disposed over the substrate and including a first power line and a second power line; organic electroluminescence elements over the multi-layer wiring layer; a partition wall over the multi-layer wiring layer; and a member over the multi-layer wiring layer, a height of the member from the substrate being greater than a height of the partition wall from the substrate, wherein the multi-layer wiring layer includes a first portion and a second portion, the organic electroluminescence elements are arrayed on the first portion, in the second portion, the first power line and the second power line intersect, and the member is positioned on the second portion without overlapping at least one of the first power line and the second power line in plan view of the substrate.Type: GrantFiled: December 15, 2015Date of Patent: April 17, 2018Assignee: JOLED INC.Inventors: Tetsuro Kondoh, Toshiaki Onimaru, Makoto Kimura, Kazuhiro Kobayashi, Yoshiki Hayashida
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Patent number: 9941344Abstract: Embodiments relate to an organic light emitting display device according to the present disclosure including: a plurality of pixels which includes red, white, blue, and green sub-pixels; driving transistor, each of which is disposed in each sub-pixel; and organic light emitting diodes, each of which is disposed corresponding to each sub-pixel, wherein a first step portion, first and second bank layers, and a first step compensation portion are disposed between the white sub-pixel and a sub-pixel adjacent thereto, thereby having an effect of suppressing a short circuit defect and a light leakage defect. In addition, an organic light emitting display device according to the present disclosure includes: red, white, blue, and green sub-pixels; at least one step portion between the sub-pixels; first and second bank layers; and a step compensation portion, thereby having an effect of suppressing a short circuit defect and a light leakage defect.Type: GrantFiled: December 15, 2015Date of Patent: April 10, 2018Assignee: LG Display Co., Ltd.Inventors: SuWoong Lee, YoungSik Jeong
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Patent number: 9936576Abstract: A method includes forming a multi-stacked electronic device having two or more electronic components, each of the electronic components includes a leadframe, the leadframes of each electronic component are physically joined together using a non-solder metal joining process to form a joint, and the joint is located outside a solder connection region.Type: GrantFiled: June 6, 2016Date of Patent: April 3, 2018Assignee: International Business Machines CorporationInventors: Ai Kiar Ang, Michael Lauri
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Method for producing an organic CMOS circuit and organic CMOS circuit protected against UV radiation
Patent number: 9935282Abstract: An organic CMOS circuit including a substrate having an N-type organic transistor and a P-type organic transistor formed thereon, the transistors respectively including a layer of N-type semiconductor material and a layer of P-type semiconductor material. A surface of each of the semiconductor material layers, opposite to the substrate, is covered with an anti-ultraviolet layer made of electrically-insulating material absorbing and/or reflecting ultra-violet rays.Type: GrantFiled: July 31, 2014Date of Patent: April 3, 2018Assignee: Commissariat a l'Energie Atomique et aux EnergiesInventors: Mohammed Benwadih, Romain Coppard, Olivier Poncelet -
Patent number: 9935293Abstract: An organic light emitting diode display includes: a substrate; a gate line on the substrate; a data line crossing the gate line; a driving voltage line extending parallel with at least one of the gate line and the data line; a first thin film transistor coupled to the gate line and the data line and comprising a first semiconductor layer; a second thin film transistor coupled to the first thin film transistor and the driving voltage line and comprising a second semiconductor layer; and an organic light emitting element coupled to the second thin film transistor, wherein at least one of the gate line, the data line, and the driving voltage line comprise a plurality of layers, and the lowest layer of the plurality of layers comprises a first metal layer made of a reflective metal.Type: GrantFiled: December 15, 2015Date of Patent: April 3, 2018Assignee: Samsung Display Co., Ltd.Inventors: Byoung Ki Kim, Hee Kyung Kim, Il Hun Seo, Young Jun Shin, Yun-Mo Chung
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Patent number: 9917109Abstract: A semiconductor device includes a wiring embedded in an insulating layer, an oxide semiconductor layer over the insulating layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate electrode provided to overlap with the oxide semiconductor layer, and a gate insulating layer provided between the oxide semiconductor layer and the gate electrode. The insulating layer is formed so that part of a top surface of the wiring is exposed. The part of the top surface of the wiring is positioned higher than part of a surface of the insulating layer. The wiring in a region exposed from the insulating layer is electrically connected to the source electrode or the drain electrode. The root-mean-square roughness of a region which is part of the surface of the insulating layer and in contact with the oxide semiconductor layer is 1 nm or less.Type: GrantFiled: March 3, 2011Date of Patent: March 13, 2018Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Teruyuki Fujii, Ryota Imahayashi