Patents Examined by Hunter L. Auyang
  • Patent number: 4625388
    Abstract: A mesa structure field effect transistor includes a semiconductor body with at least one mesa formed on a major surface and an insulating layer on the mesa and overhanging the mesa. Doped regions in the side walls of the mesa define the channel region and source of the transistor, and the semiconductor body defines and drain region. Preferential etching techniques are employed in forming the mesas and the overhanging insulator. The overhanging insulator is employed as a shadow mask in fabricating the transistor.
    Type: Grant
    Filed: December 7, 1983
    Date of Patent: December 2, 1986
    Assignee: Acrian, Inc.
    Inventor: Edward J. Rice
  • Patent number: 4619039
    Abstract: A method of manufacturing a semiconductor device having narrow, coplanar, silicon electrodes which are separated from each other by grooves or slots having a width in the submicron range. The electrodes are alternatively covered by an oxide and by an oxidation-preventing layer, such as silicon nitride. According to the invention, a first and second electrode which are both covered with one of these layers, and which enclose a third electrode covered by the other of these layers, are first interconnected inside a connection region. Two of the three electrodes are separated from the connection region by etching. By selective etching, overlapping contact windows are provided on all three electrodes, and inside the contact windows etching of the groove is omitted.
    Type: Grant
    Filed: October 4, 1984
    Date of Patent: October 28, 1986
    Assignee: U.S. Philips Corporation
    Inventors: Henricus G. R. Maas, Jan W. Slotboom, Johannes A. Appels, Kazimierz Osinski
  • Patent number: 4616399
    Abstract: A method of manufacturing an insulated gate field effect transistor has first and second impurity doping processes for forming source and drain regions. In the first doping process, an impurity is lightly doped in the source and drain forming regions in self-alignment with a silicon gate pattern and a field insulating film. Next, a heat treatment is conducted so that the side surface portions of the silicon gate pattern are converted into silicon oxide films having a predetermined thickness. Thereafter, the second doping process is conducted in which an impurity is heavily doped in each part of the source and drain forming region in self-alignment with the silicon oxide films and the field insulating film. Each of source and drain region manufactured by the method has a first part of low impurity concentration adjacent to a channel region and a second part of high impurity concentration positioned between the first part and the field insulating film.
    Type: Grant
    Filed: December 23, 1985
    Date of Patent: October 14, 1986
    Assignee: NEC Corporation
    Inventor: Hideyuki Ooka
  • Patent number: 4616403
    Abstract: A method for fabricating a metal insulator semiconductor includes first forming a substrate (10) having an array of switching elements formed therein. A plurality of deformable Indium pads (16) and (18) are then formed on the surface of the substrate and in contact with each of the switching elements. A superstrate is formed from a layer of mercury cadmium telluride (32) and a layer of dielectric insulating material (34). The superstrate is pressed down adjacent the substrate (10) with the upper surface of the conductive gates (16) and (18) contacting the lower surface of the dielectric layer (34). The deformable pads (16) and (18) conform to the lower surface of the dielectric layer (34). Epoxy (36) is then disposed in the interstices of the device to provide an adhesive force between the substrate (10) and the superstrate.
    Type: Grant
    Filed: August 31, 1984
    Date of Patent: October 14, 1986
    Assignee: Texas Instruments Incorporated
    Inventors: Eric F. Schulte, Adam J. Lewis
  • Patent number: 4616402
    Abstract: A method of manufacturing a semiconductor device with a stacked-gate-electrode structure which includes; forming source and drain regions in the surface portion of a semiconductor substrate in a spaced-apart relationship, forming a floating gate such that it overlies the channel region between the source and drain regions with a gate insulating film therebetween, and forming a control gate such that it overlies the floating gate with an insulating film therebetween. An oxidation-resistant film pattern having a predetermined opening is formed over a non-monocrystalline silicon layer. The non-monocrystalline silicon layer within the opening is selectively oxidized with the oxidation-resistant film pattern as a mask to form a separation insulating film. In this way, a floating gate layer is formed with the portion of the non-monocrystalline silicon layer insulatingly separated.
    Type: Grant
    Filed: May 2, 1985
    Date of Patent: October 14, 1986
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Seiichi Mori
  • Patent number: 4616405
    Abstract: A semiconductor device which comprises a semiconductor area having one principal surface, an emitter area and a collector area formed selectively and apart each other on the principal surface of said semiconductor area, a base area formed on said one principal surface between the emittor area and the collector area, an insulating film formed on said base area, and a high fusing point metallic film formed on said insulating film and covering said base area.
    Type: Grant
    Filed: January 14, 1985
    Date of Patent: October 14, 1986
    Assignee: Hitachi, Ltd.
    Inventor: Hideki Yasuoka
  • Patent number: 4614021
    Abstract: An improved means and method is described for providing a conductive pillar in a via between multiple layers of conductors on planar electronic structures such as integrated circuits. A lower first conductor layer is formed on the device substrate and covered with an electrically conducting etch-stop layer and a second conductor layer. The second conductor layer is masked to define the conductive via and etched selectively and anisotropically until the etch-stop layer is reached. The exposed portions of the etch-stop layer are then removed. The remaining portions of the etch-stop layer and second conductor layer together form the conductive pillar. The lower first metal layer is patterned and then covered with a planarizing layer, such as a polyimide, having a thickness at least equal to the height of the pillar. The planarizing layer is uniformly etched to expose the top of the pillar and then an upper metal layer deposited over the remaining polyimide and in contact with the top of the pillar.
    Type: Grant
    Filed: March 29, 1985
    Date of Patent: September 30, 1986
    Assignee: Motorola, Inc.
    Inventor: Terry S. Hulseweh
  • Patent number: 4610079
    Abstract: A method of dicing a semiconductor wafer in which a physical discontinuity is formed on the surface of the wafer on both sides of a dicing line to limit the spreading of cracks and chips generated during dicing. Thereafter, the semiconductor wafer is diced to separate the pellets.
    Type: Grant
    Filed: February 26, 1985
    Date of Patent: September 9, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventors: Masahiro Abe, Masafumi Miyagawa, Hatsuo Nakamura, Toshio Yonezawa
  • Patent number: 4609414
    Abstract: A particular emitter finger structure in an NPN type switching transistor. The emitter zone is divided into two lateral N type strips. In the central part are provided, on the one hand, a diffusion of N type dopants whose junction depth is small and, on the other hand, a gold diffusion substantially of the same depth as that of the junction depth of said lateral zones. Thus, any possibility of injection at the center of the emitter finger is removed, which allows higher speed transistors to be obtained.
    Type: Grant
    Filed: June 6, 1983
    Date of Patent: September 2, 1986
    Assignee: Thomson-CSF
    Inventor: Philippe Bouard
  • Patent number: 4605447
    Abstract: A plasma and heating treatment is carried out to reduce the density of charge carrier traps adjacent the interface of an insulating layer of a thermally grown silicon dioxide and a semiconductor body. During this plasma and heating treatment, the device is covered with an additional layer of silicon containing hydrogen, such as silane, for example, and this additional layer protects the insulating layer from direct bombardment of the plasma. During and/or after the plasma treatment, heating of the structure is at about 400.degree. C. or less. After the plasma and heating treatment, the additional layer is removed from at least most parts of the semiconductor device structure.
    Type: Grant
    Filed: April 26, 1984
    Date of Patent: August 12, 1986
    Assignee: U.S. Philips Corporation
    Inventors: Stanley D. Brotherton, Audrey Gill, Michael J. King
  • Patent number: 4603473
    Abstract: A method of fabricating an integrated semiconductor circuit device having a plurality of layers of circuit patterns, comprising forming the circuit pattern of at least one of the above mentioned layers by a direct exposure method using an electron beam, and forming the circuit pattern of at least one of the remaining layers by a light exposure method using a photomask.
    Type: Grant
    Filed: October 12, 1983
    Date of Patent: August 5, 1986
    Assignee: Pioneer Electronic Corporation
    Inventors: Takashi Suemitsu, Takashi Niriki
  • Patent number: 4597166
    Abstract: A semiconductor substrate has a semiconductor substrate main body having a first major surface and a second major surface opposite thereto. At least one recess is formed in the second major surface. The recess defines a semiconductor element formation region between a bottom surface thereof and the first major surface of the substrate main body. Gettering of contaminant impurities such as heavy metals can be effectively performed at the rear surface of the substrate after the formation of a semiconductor element in the element formation region.
    Type: Grant
    Filed: February 8, 1983
    Date of Patent: July 1, 1986
    Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
    Inventor: Hiroshi Iwai
  • Patent number: 4596068
    Abstract: The surface of the channel and top gates of N channel IGFETS and JFETS respectively are compensated after a high temperature processing by ion implanting boron through a protective layer. The peak impurity concentration is to occur in a sacrificial gate pad oxide layer to ensure a predictable dopant concentration in the substrate.
    Type: Grant
    Filed: December 28, 1983
    Date of Patent: June 24, 1986
    Assignee: Harris Corporation
    Inventor: Solomon F. Peters, Jr.
  • Patent number: 4594770
    Abstract: A casing for an electrical component comprises a metal lead frame having the electrical component connected thereto. A metal base member is bonded to one surface of the lead frame. A plastic housing member is bonded to a second surface of the lead frame. An adhesive seals and bonds the metal base member and plastic housing member to the lead frame so as to enclose the electrical component.
    Type: Grant
    Filed: August 9, 1984
    Date of Patent: June 17, 1986
    Assignee: Olin Corporation
    Inventor: Sheldon H. Butt
  • Patent number: 4593459
    Abstract: Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.
    Type: Grant
    Filed: December 28, 1984
    Date of Patent: June 10, 1986
    Assignee: GTE Laboratories Incorporated
    Inventors: Paul E. Poppert, Marvin J. Tabasky, Eugene O. Degenkolb
  • Patent number: 4592132
    Abstract: Inter-layer electrical shorting between layers of conductors of an integrated circuit caused by "hillocks" in the bottom layer is prevented by the use of a double layer photoresist coatings atop the insulating layer that separates the metal layers. The double layer photoresist insures that irregularities in the dielectric layer caused by hillocks in the underlying insulating layer do not cause a break in the photoresist and a subsequent undesired etching of a spurious "via" through the dielectric layer.
    Type: Grant
    Filed: December 7, 1984
    Date of Patent: June 3, 1986
    Assignee: Hughes Aircraft Company
    Inventors: William W. Y. Lee, Gareth L. Shaw, James W. Clayton, deceased, Denise Bachino, administrator
  • Patent number: 4590667
    Abstract: A wafer divided into rows of abutted end-to-end dice (i.e., semiconductor chips) is placed on a thin, non-elastic membrane and drawn tightly over a knife-edge to successively separate each row of dice from the membrane. The dice are then attached to individual leadframes directly or are picked up by a vacuum fixture and carried to a position where they are secured to the leadframes and are wire bonded. After bonding, the components are assembled into finished subassemblies. In one embodiment, LED lamps are fabricated. A reflector is secured to each leadframe over the die positioned thereon, and the leadframe, die and reflector are molded into a lamp subassembly, which is used to form a larger lamp or display fixture.
    Type: Grant
    Filed: August 22, 1984
    Date of Patent: May 27, 1986
    Assignee: General Instrument Corporation
    Inventor: Ralph E. Simon
  • Patent number: 4590663
    Abstract: N-channel devices are fabricated with lightly doped drain/source extensions in a CMOS process, without the requirement of an extra mask level. A merged mask technique uses an oversized version of the N-channel gates, expanded by two alignment tolerances per side, combined with the regular N+ source/drain mask. The oversized gate photoresist prevents the heavy N+ source/drain implant from counterdoping the previously introduced lightly doped drain blanket implant. In the P-channel regions the N-type LDD extensions are counterdoped by the regular P+ source/drain implant. This high-voltage process provides 20 V parts with 4 micron geometries, scalable to other voltages.
    Type: Grant
    Filed: February 23, 1983
    Date of Patent: May 27, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Roger A. Haken
  • Patent number: 4589195
    Abstract: An improved high power semiconductor device and manufacturing method are described wherein one or more die are assembled to one electrode having a heat transfer face and additional insulated electrodes, said electrode having bent up and bent over portions forming high current terminals and control terminals such that the current terminals and control terminals lie in different planes and such that terminal spacings satisfy Underwriters Laboratory recommendations. The die and electrode assembly is partly encapsulated preferably in plastic. The current terminals are diagonally located to facilitate use of standard bus bar arrangements with different device orientations. Connection nuts are movably retained to limit transfer of tightening torque to the plastic body. Choices of materials are described.
    Type: Grant
    Filed: January 17, 1985
    Date of Patent: May 20, 1986
    Assignee: Motorola, Inc.
    Inventors: Jerry M. Du Bois, Keith G. Spanjer
  • Patent number: 4589196
    Abstract: Metal contacts and interconnections for semiconductor integrated circuits are formed by a process using direct-reacted silicide to increase step or sidewall coverage. First a thin layer of titanium or other refractory metal is deposited, extending into a contact hole, then polysilicon is deposited and a preferential etch removes all of the polysilicon except on the vertical sides of steps or apertures. A second thin layer of titanium is deposited, then a heat treatment forms silicide to create conductive sidewalls or a plug. Metal contacts then engage the direct-reacted silicide rather than relying upon step coverage.
    Type: Grant
    Filed: October 11, 1984
    Date of Patent: May 20, 1986
    Assignee: Texas Instruments Incorporated
    Inventor: Dirk N. Anderson