Patents Examined by Huy Duong
  • Patent number: 11915116
    Abstract: An arithmetic apparatus used for a neural network includes a plurality of digital-time conversion circuits connected in series and a time-digital conversion circuit connected to a last digital-time conversion circuit in the series. Each of the digital-time conversion circuits is configured to delay a first input time signal by a variable amount, delay a second input time signal by a fixed amount, and output the delayed first and second input time signals respectively as either first and second output time signals or second and first output time signals, in accordance with the input data. The time-digital conversion circuit is configured to generate a digital output signal by comparing first and second output time signals from the last digital-time conversion circuit.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: February 27, 2024
    Assignee: Kioxia Corporation
    Inventors: Daisuke Miyashita, Shouhei Kousai
  • Patent number: 11899741
    Abstract: A memory device includes a memory configured to store input data and filter data for a convolution operation, and a function processor configured to, in response to a read command of at least a portion of data from among the input data and the filter data, transform the at least a portion of the data based on a parameter of the convolution operation during a clock cycle corresponding to the read command and output a corresponding transformation result as transformed data.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: February 13, 2024
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyung-Dal Kwon, Seung Wook Lee
  • Patent number: 11899745
    Abstract: Disclosed herein includes a system, a method, and a device for processing and converting data using matrix operations. Circuitry can partition an input of a first data format across a plurality of lookup tables each residing in a respective memory. The circuitry can access weight information from a load store memory, and the partitioned input on a per column basis from the plurality of lookup tables. The circuitry can perform a number of multiply-accumulate (MAC) operations per cycle between the weight information from the load store memory and the partitioned input read on a per column basis from the plurality of lookup tables. The number of MAC operations performed per cycle can correspond to a total number of columns of the plurality of lookup tables. The circuitry can generate, responsive to the MAC operations on the partitioned input, a plurality of outputs in a second data format.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: February 13, 2024
    Assignee: Meta Platforms Technologies, LLC
    Inventors: Alagappan Valliappan, Ganesh Venkatesh, Pierce I-Jen Chuang
  • Patent number: 11886832
    Abstract: An operation device includes a quantizer circuit, a buffer circuit, a convolution core circuit and a multiply-add circuit. The quantizer circuit receives first feature data and performs asymmetric uniform quantization on the first feature data to obtain and store in the buffer circuit second feature data. The quantizer circuit further receives a first weighting coefficient and performs symmetric uniform quantization on the first weighting coefficient to obtain and store in the buffer circuit a second weight coefficient. The convolution core circuit performs a convolution operation on the initial operation result, an actual quantization scale factor and an actual bias value to obtain a final operation result.
    Type: Grant
    Filed: December 28, 2020
    Date of Patent: January 30, 2024
    Assignee: SIGMASTAR TECHNOLOGY LTD.
    Inventors: Xiaofeng Li, Chengwei Zheng, Bo Lin
  • Patent number: 11886505
    Abstract: A function approximation system is disclosed for determining output floating point values of functions calculated using floating point numbers. Complex functions have different shapes in different subsets of their input domain, making them difficult to predict for different values of the input variable. The function approximation system comprises an execution unit configured to determine corresponding values of a given function given a floating point input to the function; a plurality of look up tables for each function type; a correction table of values which determines if corrections to the output value are required; and a table selector for finding an appropriate table for a given function.
    Type: Grant
    Filed: April 5, 2022
    Date of Patent: January 30, 2024
    Assignee: GRAPHCORE LIMITED
    Inventors: Jonathan Mangnall, Stephen Felix
  • Patent number: 11874897
    Abstract: Systems, devices, and methods related to a Deep Learning Accelerator and memory are described. An integrated circuit may be configured to perform at least computations on matrix operands and configured with: random access memory configured to store instructions executable by the Deep Learning Accelerator and store matrices of an Artificial Neural Network; a connection between the random access memory and the Deep Learning Accelerator; and an interface to a memory controller. The interface may be configured to facilitate access to the random access memory by the memory controller. In response to an indication provided in the random access memory, the Deep Learning Accelerator may execute the instructions to apply input that is stored in the random access memory to the Artificial Neural Network, generate output from the Artificial Neural Network, and store the output in the random access memory.
    Type: Grant
    Filed: April 9, 2020
    Date of Patent: January 16, 2024
    Assignee: Micron Technology, Inc.
    Inventors: Poorna Kale, Jaime Cummins
  • Patent number: 11876899
    Abstract: A random number generator includes a static random number generator, a dynamic entropy source, a counter and a combining circuit. The static random number generator includes an initial random number pool and a static random number pool to output a static random number sequence from one thereof the initial random number pool and the static random number pool. The dynamic entropy source is used to generate a dynamic entropy bit. The counter is used to generate a dynamic random number sequence according to the dynamic entropy bit. The combining circuit is used to output a true random number sequence to a lively random number pool according to the static random number sequence and the dynamic random number sequence. The static random number pool is updated when the lively random number pool is fully updated.
    Type: Grant
    Filed: July 22, 2020
    Date of Patent: January 16, 2024
    Assignee: PUFsecurity Corporation
    Inventors: Meng-Yi Wu, Chi-Yi Shao, Ching-Sung Yang
  • Patent number: 11836463
    Abstract: A neural network device includes a shift register circuit, a control circuit, and a processing circuit. The shift register circuit includes registers configured to, in each cycle of cycles, transfer stored data to a next register and store new data received from a previous register to a current register. The control circuit is configured to sequentially input data of input activations included in an input feature map into the shift register circuit in a preset order. The processing circuit, includes crossbar array groups that receive input activations from at least one of the registers and perform a multiply-accumulate (MAC) operation with respect to the received input activation and weights, is configured to accumulate and add at least some operation results output from the crossbar array groups in a preset number of cycles to obtain an output activation in an output feature map.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: December 5, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Minje Kim, Soonwan Kwon
  • Patent number: 11829731
    Abstract: A modular multiplication circuit includes a main operation circuit, a look-up table, and an addition unit. The main operation circuit updates a sum value and a carry value according to 2iA corresponding to a first operation value A and m bits of a second operation value B currently under operation, m is a positive integer, i is from 0 to m?1. The look-up table records values related to a modulus, and selects one of the values as a look-up table output value according to the sum value. The addition unit updates the sum value and the carry value according to the look-up table output value and outputs the updated sum value and the updated carry value to the main operation circuit. The modular multiplication circuit updates the sum value and the carry value in a recursive manner by using m different bits of the second operation value B.
    Type: Grant
    Filed: December 27, 2021
    Date of Patent: November 28, 2023
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chia-Hsiang Yang, Liang-Hsin Lin, Yu-Ling Kang, Li-Chi Su
  • Patent number: 11822898
    Abstract: A semiconductor memory device includes a plurality of memory bank groups configured to be accessed in parallel; an internal memory bus configured to receive external data from outside the plurality of memory bank groups; and a first computation circuit configured to receive internal data from a first memory bank group of the plurality of memory bank groups during each first period of a plurality of first periods, receive the external data through the internal memory bus during each second period of a plurality of second periods, the second period being shorter than the first period, and perform a processing in memory (PIM) arithmetic operation on the internal data and the external data during each second period.
    Type: Grant
    Filed: December 10, 2021
    Date of Patent: November 21, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shinhaeng Kang, Seongil O
  • Patent number: 11741187
    Abstract: A calculation device includes a memory and one or more processors coupled to the memory and configured to alternately update, for elements each associated with first and second variables, the first and second variables, sequentially for unit times from an initial time to an end time. In an updating process for each unit time, the one or more processors are configured to: update, for each of the elements, the first variable based on the second variable; when the first variable is smaller than a first value, change the first variable to the first value and change the second variable to a third value; when the first variable is greater than a second value, change the first variable to the second value and change the second variable to the third value; and add an acceleration value calculated by a predetermined computation to the second variable.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: August 29, 2023
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Taro Kanao, Hayato Goto, Ryo Hidaka, Kosuke Tatsumura
  • Patent number: 11726746
    Abstract: This application describes hybrid hardware accelerators, systems, and apparatus for performing various computations in neural network applications using the same set of hardware resources. An example accelerator may include weight selectors, activation input interfaces, and a plurality of Multiplier-Accumulation (MAC) circuits organized as a plurality of MAC lanes Each of the plurality of MAC lanes may be configured to: receive a control signal indicating whether to perform convolution or vector operations; receive one or more weights according to the control signal; receive one or more activations according to the control signal; and generate output data based on the one or more weights and the one or more input activations according to the control signal and feed the output data into an output buffer. Each of the plurality of MAC lanes includes a plurality of multiplier circuits and a plurality of adder-subtractor circuits.
    Type: Grant
    Filed: September 14, 2022
    Date of Patent: August 15, 2023
    Assignee: Moffett International Co., Limited
    Inventors: Xiaoqian Zhang, Zhibin Xiao, Changxu Zhang, Renjie Chen
  • Patent number: 11709911
    Abstract: Described herein are systems and methods that increase the utilization and performance of computational resources, such as storage space and computation time, thereby, reducing computational cost. Various embodiments of the invention provide for a hardware structure that allows both streaming of source data that eliminates redundant data transfer and allows for in-memory computations that eliminate requirements for data transfer to and from intermediate storage. In certain embodiments, computational cost is reduced by using a hardware structure that enables mathematical operations, such as element-wise matrix multiplications employed by convolutional neural networks, to be performed automatically and efficiently.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: July 25, 2023
    Assignee: Maxim Integrated Products, Inc.
    Inventors: Mark Alan Lovell, Robert Michael Muchsel
  • Patent number: 11693662
    Abstract: Systems and methods for configuring a reduced instruction set computer processor architecture to execute fully homomorphic encryption (FHE) logic gates as a streaming topology. The method includes parsing sequential FHE logic gate code, transforming the FHE logic gate code into a set of code modules that each have in input and an output that is a function of the input and which do not pass control to other functions, creating a node wrapper around each code module, configuring at least one of the primary processing cores to implement the logic element equivalents of each element in a manner which operates in a streaming mode wherein data streams out of corresponding arithmetic logic units into the main memory and other ones of the plurality arithmetic logic units.
    Type: Grant
    Filed: January 15, 2020
    Date of Patent: July 4, 2023
    Assignee: CORNAMI INC.
    Inventors: Morris Jacob Creeger, Tianfang Liu, Frederick Furtek, Paul L. Master
  • Patent number: 11669304
    Abstract: According to one embodiment, an arithmetic device includes: a first input terminal; a second input terminal; an output terminal; a first logical shifter; a second logical shifter; a third logical shifter; a first AND gate; a second AND gate; a first multiplexer; a third AND gate; a first adder; a fourth logical shifter; a second multiplexer; a second adder; a first arithmetic shifter; a second arithmetic shifter; a third arithmetic shifter; a third multiplexer; a fourth multiplexer; and a fifth multiplexer.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: June 6, 2023
    Assignee: Kioxia Corporation
    Inventor: Mikio Shiraishi
  • Patent number: 11662978
    Abstract: A modular operation circuit includes a controller, a modular multiplier and a modular adder. The controller divides a first number into K segments. The modular multiplier performs modular multiplication operations and the modular adder performs modular addition operations to the K segments in (K?1) iterations for deriving a remainder of a division of the first number by a second number.
    Type: Grant
    Filed: November 25, 2020
    Date of Patent: May 30, 2023
    Assignee: PUFsecurity Corporation
    Inventor: Wen-Ching Lin
  • Patent number: 11657238
    Abstract: A compute-in-memory bitcell is provided that includes a pair of cross-coupled inverter for storing a stored bit. The compute-in-memory bitcell includes a logic gate for multiplying the stored bit with an input vector bit. An output node for the logic gate connects to a second plate of a capacitor. A first plate of the capacitor connects to a read bit line.
    Type: Grant
    Filed: January 31, 2020
    Date of Patent: May 23, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Ankit Srivastava, Seyed Arash Mirhaj, Guoqing Miao, Seyfi Bazarjani
  • Patent number: 11650793
    Abstract: A processing element, a neural processing device including the same, and a method for calculating thereof are provided. The processing element includes a weight register configured to receive and store weights, an input activation register configured to store input activations, a flexible multiplier configured to receive the weight and the input activation, to perform a multiplication calculation in a first precision or a second precision different from the first precision according to a mode signal, occurrence of an overflow, and occurrence of an underflow, and to generates result data; and a saturating adder configured to receive the result data and generate subtotals.
    Type: Grant
    Filed: March 25, 2022
    Date of Patent: May 16, 2023
    Assignee: Rebellions Inc.
    Inventor: Jinwook Oh
  • Patent number: 11631002
    Abstract: An information processing device includes: a processor configured to: calculate a combination of t and q minimizing a computation time when q computation cores compute convolution between first matrices and second matrices of t-row t-column with Winograd algorithm in parallel, where a total number of elements of the first and second matrices does not exceed a number of sets of data that can be stored in each of q storage areas of a register, and the q computation cores correspond to the q storage areas; and output a program for causing a computing machine including the q computation cores and the register to execute a process including: storing the first and second matrices in each of the q storage areas with a calculated combination of t and q, and computing convolution between the first matrix and the second matrix with the Winograd algorithm by each of the q computation cores.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: April 18, 2023
    Assignee: FUJITSU LIMITED
    Inventor: Toshihiro Shimizu
  • Patent number: 11620106
    Abstract: A combined adder for N logical bits to produce a sum from a first addend having N first addend bits and a second addend having N second addend bits. A least significant adder produces a segment sum of the least significant bits and a carry out. Segment adder pairs are used for each higher order of significant sums. One segment adder produces a segment sum portion, and the other produces an incremented segment sum portion. Carry logic associated with each segment is utilized with a multiplexer to select the incremented segment sum portion or the segment sum portion. The selected segment sum portions are assembled with a most significant carry out to produce the sum.
    Type: Grant
    Filed: December 16, 2020
    Date of Patent: April 4, 2023
    Inventor: Makia S Powell