Patents Examined by Huy Duong
  • Patent number: 11409836
    Abstract: A computer-implemented optimization problem arithmetic method includes determining, based on management information indicating a partition mode that defines a logically divided state of each of a plurality of arithmetic circuits and utilization information relating to each of the plurality of arithmetic circuits, a partition mode of each of the plurality of arithmetic circuits, receiving a combinatorial optimization problem, selecting, based on information relating to scale or requested accuracy of the combinatorial optimization problem and the determined partition mode of each of the plurality of arithmetic units, a first arithmetic circuit from among the plurality of arithmetic circuits, and causing the selected first arithmetic circuit to execute arithmetic operation of the combinatorial optimization problem based on a first partition mode determined as the partition mode of the first arithmetic circuit.
    Type: Grant
    Filed: September 17, 2019
    Date of Patent: August 9, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroshi Yagi, Noriyuki Itakura, Noriaki Shimada
  • Patent number: 11403068
    Abstract: Apparatus and associated methods relate to determining a natural exponent from a digital word input by splitting the digital word, and retrieving a precalculated and predetermined value from a data store at an address defined by the first word. In an illustrative example, the retrieved value may be a hyperbolic sum. The hyperbolic sum may be multiplied by the second word. The hyperbolic sum may be scaled, and summed with the multiplication result to generate a scaled exponential value. The scaled exponential value may be scaled to produce an exponential value representing eX. In various examples, the digital word input may be in a fixed point or a floating point format, or converted therebetween. In various embodiments, the data store may be a lookup table. Various examples may provide a compact and versatile architecture for determining a natural exponent with minimized hardware resources.
    Type: Grant
    Filed: August 24, 2020
    Date of Patent: August 2, 2022
    Assignee: XILINX, INC.
    Inventor: Stefano Cappello
  • Patent number: 11379673
    Abstract: An analog vector-matrix multiplication circuit is achieved by using a programmable storage device array. In a programmable semiconductor device array, gates of all of programmable semiconductor devices of each row are all connected to the same analog voltage input end. M rows of programmable semiconductor devices are correspondingly connected to M analog voltage input ends. Drains (or sources) of all of programmable semiconductor devices of each column are all connected to the same bias voltage input end. N columns of programmable semiconductor devices are correspondingly connected to N bias voltage input ends. Sources (or drains) of all of programmable semiconductor devices of each column are all connected to the same analog current output end. The N columns of programmable semiconductor devices are correspondingly connected to N analog current output ends.
    Type: Grant
    Filed: February 1, 2021
    Date of Patent: July 5, 2022
    Assignee: BEIJING ZHICUN WITIN TECHNOLOGY CORPORATION LIMITED
    Inventor: Shaodi Wang
  • Patent number: 11340867
    Abstract: Certain aspects provide methods and apparatus for binary computation. An example circuit for such computation generally includes a memory cell having at least one of a bit-line or a complementary bit-line; a computation circuit coupled to a computation input node of the circuit and the bit-line or the complementary bit-line; and an adder coupled to the computation circuit, wherein the computation circuit comprises a first n-type metal-oxide-semiconductor (NMOS) transistor coupled to the memory cell, and a first p-type metal-oxide-semiconductor (PMOS) transistor coupled to the memory cell, drains of the first NMOS and PMOS transistors being coupled to the adder, wherein a source of the first PMOS transistor is coupled to a reference potential node, and wherein a source of the first NMOS transistor is coupled to the computation input node.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: May 24, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Xia Li, Zhongze Wang, Periannan Chidambaram
  • Patent number: 11334646
    Abstract: An information processing apparatus includes: a memory; and a processor coupled to the memory and configured to: hold values of a plurality of state variables included in an evaluation function representing energy, and outputs, every certain number of trials, the values of the plurality of state variables; compute, when a state transition occurs in response to changing of one of the values of the plurality of state variables, an energy change value for each state transition based on a weight value selected based on an update index value; and determine a first offset value based on a plurality of the energy change values such that at least one of the state transitions is allowed, outputs a plurality of first evaluation values obtained by adding the first offset value to the plurality of energy change values, and outputs, every certain number of trials, the first offset value.
    Type: Grant
    Filed: February 20, 2020
    Date of Patent: May 17, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Aki Dote, Hirotaka Tamura
  • Patent number: 11328015
    Abstract: A function approximation system is disclosed for determining output floating point values of functions calculated using floating point numbers. Complex functions have different shapes in different subsets of their input domain, making them difficult to predict for different values of the input variable. The function approximation system comprises an execution unit configured to determine corresponding values of a given function given a floating point input to the function; a plurality of look up tables for each function type; a correction table of values which determines if corrections to the output value are required; and a table selector for finding an appropriate table for a given function.
    Type: Grant
    Filed: April 26, 2019
    Date of Patent: May 10, 2022
    Assignee: Graphcore Limited
    Inventors: Jonathan Mangnall, Stephen Felix
  • Patent number: 11327754
    Abstract: Methods and apparatus for approximation using polynomial functions are disclosed. In one embodiment, a processor comprises decoding and execution circuitry. The decoding circuitry is to decode an instruction, where the instruction comprises a first operand specifying an output location and a second operand specifying a plurality of data element values to be computed. The execution circuitry is to execute the decoded instruction. The execution includes to compute a result for each of the plurality of data element values using a polynomial function to approximate a complex function, where the computation uses coefficients stored in a lookup location for the complex function, and where data element values within different data element value ranges use different sets of coefficients. The execution further includes to store results of the computation in the output location.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: May 10, 2022
    Assignee: INTEL CORPORATION
    Inventors: Jorge Parra, Dan Baum, Robert S. Chappell, Michael Espig, Varghese George, Alexander Heinecke, Christopher Hughes, Subramaniam Maiyuran, Prasoonkumar Surti, Ronen Zohar, Elmoustapha Ould-Ahmed-Vall
  • Patent number: 11307826
    Abstract: A memory device is provided. The memory device includes: a memory cell configured to store weight data, a buffer memory configured to read the weight data from the memory cell, an input/output pad configured to receive input data and a multiply-accumulate (MAC) operator configured to receive the weight data from the buffer memory and receive the input data from the input/output pad to perform a convolution operation of the weight data and the input data, wherein the input data is provided to the MAC operator during a first period, and wherein the MAC operator performs the convolution operation of the weight data and the input data during a second period overlapping with the first period.
    Type: Grant
    Filed: September 23, 2019
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Ga Ram Kim
  • Patent number: 11301211
    Abstract: A differential mixed-signal logic processor is provided. The differential mixed-signal logic processor includes a plurality of mixed-signal multiplier branches for multiplication of an analog value A and a N-bit digital value B. Each of the plurality of mixed-signal multiplier branches include a first capacitor connected across a second capacitor and a third capacitor to provide a differential output across the second and third capacitors. A capacitance of the first capacitor is equal to half a capacitance of the second and third capacitors.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: April 12, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Seyoung Kim, Mingu Kang, Kyu-hyoun Kim, Seonghoon Woo
  • Patent number: 11288040
    Abstract: Systems, apparatuses and methods may provide for technology that conduct a first alignment between a plurality of floating-point numbers based on a first subset of exponent bits. The technology may also conduct, at least partially in parallel with the first alignment, a second alignment between the plurality of floating-point numbers based on a second subset of exponent bits, where the first subset of exponent bits are LSBs and the second subset of exponent bits are MSBs. In one example, technology adds the aligned plurality of floating-point numbers to one another. With regard to the second alignment, the technology may also identify individual exponents of a plurality of floating-point numbers, identify a maximum exponent across the individual exponents, and conduct a subtraction of the individual exponents from the maximum exponent, where the subtraction is conducted from MSB to LSB.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: March 29, 2022
    Assignee: Intel Corporation
    Inventors: Himanshu Kaul, Mark Anders
  • Patent number: 11281428
    Abstract: A data processing apparatus is provided to convert a plurality of signed digits to an output value, the data processing apparatus comprising: receiver circuitry to receive, at each of a plurality of iterations, a signed digit from the plurality of signed digits, and previous intermediate data. Conversion circuitry performs a negative-output conversion from the signed digit to an unsigned digit, such that the output value comprising the unsigned digit is negative. Concatenation circuitry concatenate bits of the unsigned digit and bits of the previous intermediate data to produce updated intermediate data and output circuitry provides the updated intermediate data as the previous intermediate data of a next iteration. After the plurality of iterations, the output circuitry outputs at least part of the updated intermediate data as the output value.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: March 22, 2022
    Assignee: ARM LIMITED
    Inventor: Javier Diaz Bruguera
  • Patent number: 11277120
    Abstract: As part of a signal processing event, the maximum frequency of an input signal can be determined with a processor. The maximum frequency can be compared to a value generated with a decimator/interpolator. Based on the comparison, the sampling rate for sampling the input signal with the processor can be set as part of the digital signal processing event. The sampling rate can be adjusted as the frequency of the input signal varies during the signal processing event.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: March 15, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Ivan James Reedman
  • Patent number: 11269630
    Abstract: Disclosed embodiments relate to an interleaved pipeline of floating-point (FP) adders. In one example, a processor is to execute an instruction specifying an opcode and locations of a M by K first source matrix, a K by N second source matrix, and a M by N destination matrix, the opcode indicating execution circuitry, for each FP element (M, N) of the destination matrix, is to: launch K instances of a pipeline having a first, MULTIPLY stage, during which a FP element (M, K) of the first source matrix and a corresponding FP element (K, N) of the second source matrix are multiplied; concurrently, in an EXPDIFF stage, determine an exponent difference between the product and a previous FP value of the element (M, N) of the destination matrix; and in a second, ADD-BYPASS stage, accumulate the product with the previous FP value and, concurrently, bypassing the accumulated sum to a subsequent pipeline instance.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 8, 2022
    Assignee: INTEL CORPORATION
    Inventors: Simon Rubanovich, Amit Gradstein, Zeev Sperber
  • Patent number: 11250106
    Abstract: A matrix processing apparatus having a three-dimensional slice access memory and an input-/output block. The slice access memory includes cells organized into cell slices, each slice storing an entire selected data matrix. The three-dimensional slice access memory is configured to allow read/write access to the entire data matrix at the same time. The input/output block is connected to the three-dimensional slice access memory and is configured to format data into a format acceptable to the three-dimensional slice access memory.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: February 15, 2022
    Inventors: Dmitri Pescianschi, Ilya Sorokin
  • Patent number: 11250104
    Abstract: A device configured to emulate a quadrilateral lattice correlithm object generator includes multiple processing stages that operate together to output a quadrilateral lattice correlithm object. A quadrilateral lattice correlithm object has a quadrilateral geometric shape and is formed by at least four sub-lattice correlithm objects that are some number of bits away from each other in n-dimensional space.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: February 15, 2022
    Assignee: Bank of America Corporation
    Inventor: Patrick N. Lawrence
  • Patent number: 11245416
    Abstract: Massively parallel, block-based encoding and decoding technology that includes an encoded block format uses a plurality of processing cores to perform block-based encoding and decoding operations. The encoded block format includes a header and a payload. The encoded block format's headers represent unique single-Byte and multi-Byte event parameters that occur in the original data block from which each encoded block was generated. The encoded block format's payloads represent a sequence of single-Byte and multi-Byte events using tokens that associate each event with its corresponding parameter(s). Metadata can include an array of encoded block sizes that support random access.
    Type: Grant
    Filed: June 20, 2017
    Date of Patent: February 8, 2022
    Assignee: ANACODE LABS, INC.
    Inventor: Albert W Wegener
  • Patent number: 11244026
    Abstract: A computer-implemented optimization problem arithmetic method includes, receiving a combinatorial optimization problem, selecting a first arithmetic circuit from among a plurality of arithmetic circuits based on a scale or a requested accuracy of the combinatorial optimization problem and a partition mode that defines logically divided states of each of the plurality of arithmetic circuits, and causing the first arithmetic circuit to execute an arithmetic operation of the combinatorial optimization problem.
    Type: Grant
    Filed: September 12, 2019
    Date of Patent: February 8, 2022
    Assignee: FUJITSU LIMITED
    Inventors: Hiroshi Kondou, Hiroshi Yagi, Noriyuki Itakura, Noriaki Shimada
  • Patent number: 11226763
    Abstract: The invention is notably directed at a device for high-dimensional computing comprising an associative memory module. The associative memory module comprises one or more planar crossbar arrays. The one or more planar crossbar arrays comprise a plurality of resistive memory elements. The device is configured to program profile vector elements of profile hypervectors as conductance states of the resistive memory elements and to apply query vector elements of query hypervectors as read voltages to the one or more crossbar arrays. The device is further configured to perform a distance computation between the profile hypervectors and the query hypervectors by measuring output current signals of the one or more crossbar arrays. The invention further concerns a related method and a related computer program product.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: January 18, 2022
    Assignees: International Business Machines Corporation, ETH ZURICH (EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZURICH)
    Inventors: Manuel Le Gallo-Bourdeau, Kumudu Geethan Karunaratne, Giovanni Cherubini, Abu Sebastian, Abbas Rahimi, Luca Benini
  • Patent number: 11170069
    Abstract: According to one embodiment, a calculating device includes a processor. The processor acquires a data set {s} and repeats a processing procedure. The processing procedure includes first and second variable updates. The first variable update includes updating an ith entry of a first variable xi by adding a first function to the ith entry of the first variable xi. The ith entry of the first variable xi is one of a first variable set {x}. A variable of the first function includes at least a part of a second variable set {y}. The second variable update includes updating an ith entry of a second variable yi by adding a second function and a third function to the ith entry of the second variable yi. The ith entry of the second variable yi is one of the second variable set {y}. The processor outputs at least a fourth function.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: November 9, 2021
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taro Kanao, Hayato Goto, Kosuke Tatsumura
  • Patent number: 11126404
    Abstract: A device for providing a random number generator is provided. The device may include a true random number generator, at least one deterministic random number generator, and an exclusive OR logic function. The TRNG has an output and the at least one DRNG has an output. The exclusive OR logic function has a first input coupled to the output of the TRNG and a second input coupled to the output of the at least one DRNG, and an output for providing a random number. The TRNG and the at least one DRNG may include separate and independent entropy sources. A method for generating a random number is also provided.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: September 21, 2021
    Assignee: NXP B.V.
    Inventors: Bruce Murray, Mario Lamberger