Patents Examined by Hyun Nam
  • Patent number: 11775298
    Abstract: Methods for frequency scaling for per-core accelerator assignments and associated apparatus. A processor includes a CPU (central processing unit) having multiple cores that can be selectively configured to support frequency scaling and instruction extensions. Under this approach, some cores can be configured to support a selective set of AVX instructions (such as AVX3/5G-ISA instructions) and/or AMX instructions, while other cores are configured to not support these AVX/AMX instructions. In one aspect, the selective AVX/AMX instructions are implemented in one or more ISA extension units that are separate from the main processor core (or otherwise comprises a separate block of circuitry in a processor core) that can be selectively enabled or disabled. This enables cores having the separate unit(s) disabled to consume less power and/or operate at higher frequencies, while supporting the selective AVX/AMX instructions using other cores.
    Type: Grant
    Filed: July 20, 2020
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Stephen T. Palermo, Srihari Makineni, Shubha Bommalingaiahnapallya, Neelam Chandwani, Rany T. Elsayed, Udayan Mukherjee, Lokpraveen Mosur, Adwait Purandare
  • Patent number: 11768781
    Abstract: An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.
    Type: Grant
    Filed: May 27, 2022
    Date of Patent: September 26, 2023
    Assignee: Intel Corporation
    Inventors: Niranjan L. Cooray, Abhishek R. Appu, Altug Koker, Joydeep Ray, Balaji Vembu, Pattabhiraman K, David Puffer, David J. Cowperthwaite, Rajesh M. Sankaran, Satyeshwar Singh, Sameer Kp, Ankur N. Shah, Kun Tian
  • Patent number: 11748099
    Abstract: The disclosure discloses a method for executing instructions, a device and a computer readable storage medium. The detailed implementation includes: obtaining a first memory access instruction for execution, in which the first memory access instruction includes a first address range of a memory to be accessed; in response to detecting a predetermined instruction for monitoring an accessed address range of the memory, executing the predetermined instruction to obtain a remaining address range not accessed by the first memory access instruction in the first address range; comparing the remaining address range with a second address range included in a second memory access instruction to be executed; and suspending execution of the second memory access instruction in response to the remaining address range at least partially overlapping with the second address range.
    Type: Grant
    Filed: July 16, 2021
    Date of Patent: September 5, 2023
    Assignee: BEIJING BAIDU NETCOM SCIENCE AND TECHNOLOGY, CO., LTD.
    Inventors: Chao Tang, Xueliang Du
  • Patent number: 11748283
    Abstract: Embodiments described herein provide techniques to facilitate scalable interrupts and workload submission for a virtualized graphics processor. The techniques include memory-based interrupt reporting and shared work queue submission for multiple software domains.
    Type: Grant
    Filed: June 3, 2022
    Date of Patent: September 5, 2023
    Assignee: Intel Corporation
    Inventors: David Puffer, Ankur Shah, Niranjan Cooray, Bryan White, Balaji Vembu, Hema Chand Nalluri, Kritika Bala
  • Patent number: 11749335
    Abstract: A memory module without a controller and without a built-in power supply and a memory controller thereof are provided. The memory module includes a connection portion, a first non-volatile memory chip, and a second non-volatile memory chip. The memory controller of the motherboard accesses the first non-volatile memory chip by a native interface of the first non-volatile memory chip through the connection portion. The second non-volatile memory chip is configured to store at least one pointer of a meta data of the first non-volatile memory chip. The memory type of the second non-volatile memory chip is different from the memory type of the first non-volatile memory chip. The memory controller accesses the pointer stored in the second non-volatile memory chip through the connection portion.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: September 5, 2023
    Assignees: SHANDONG STORAGE WINGS ELECTRONICS TECHNOLOGY CO., LTD
    Inventor: Jianzhong Bi
  • Patent number: 11740899
    Abstract: Methods, systems, and devices for in-memory associative processing are described. An apparatus may receive a set of instructions that indicate a first vector and a second vector as operands for a computational operation. The apparatus may select, from a set of vector mapping schemes, a vector mapping scheme for performing the computational operation using associative processing. The apparatus may write the first vector and the second vector to a set of planes each comprising an array of content-addressable memory cells based on the selected vector mapping scheme.
    Type: Grant
    Filed: January 18, 2022
    Date of Patent: August 29, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Sean S. Eilert, Ameen D. Akel, Justin Eno, Brian Hirano
  • Patent number: 11730325
    Abstract: Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include streaming interconnects which transmit streaming data using two different modes: circuit switching and packet switching. Circuit switching establishes reserved point-to-point communication paths between endpoints in the interconnect which routes data in a deterministic manner. Packet switching, in contrast, transmits streaming data that includes headers for routing data within the interconnect in a non-deterministic manner. In one embodiment, the streaming interconnects can have one or more ports configured to perform circuit switching and one or more ports configured to perform packet switching.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 22, 2023
    Assignee: XILINX, INC.
    Inventors: Peter McColgan, Goran Hk Bilski, Juan J. Noguera Serra, Jan Langer, Baris Ozgul, David Clarke
  • Patent number: 11720358
    Abstract: Embedded systems and methods of starting an embedded system are disclosed. A method of starting an embedded system includes executing first instructions, distinct from instructions of an operating system of the embedded system. The method further includes causing the storage of at least one application into a non-volatile memory in response to executing the first instructions.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: August 8, 2023
    Assignee: PROTON WORLD INTERNATIONAL N.V.
    Inventors: Youssef Ahssini, Guy Restiau
  • Patent number: 11714776
    Abstract: A system-on-chip (SoC) may be configured to enable a Multi-Chip Daisy Chain Topology using peripheral component interface express (PCIe). The SoC may include a processor, a local memory, a root complex operably connected to the processor and the local memory, and a multi-function endpoint controller. The root complex may obtain forwarding information to configure routing of transactions to one or more PCIe endpoint functions or to the local memory. The root complex may initialize, based on the forwarding information, access between a host and the one or more PCIe endpoint functions. The multi-function endpoint controller may obtain a descriptor and endpoint information to configure outbound portals for transactions to at least one remote host. The multi-function endpoint controller may establish a communication path between the host and a function out of a plurality of functions.
    Type: Grant
    Filed: December 29, 2021
    Date of Patent: August 1, 2023
    Assignee: Texas Instmments Incorporated
    Inventors: Kishon Vijay Abraham Israel Vijayponraj, Sriramakrishnan Govindarajan, Mihir Narendra Mody
  • Patent number: 11714643
    Abstract: Embedded systems and methods of reading or writing data or instructions of at least one application in a non-volatile memory are disclosed. A method includes reading or writing data or instructions of at least one application in a non-volatile memory of an embedded system. The data or instructions transit through a memory area and are interpreted by a distinct program of an operating system of the embedded system.
    Type: Grant
    Filed: December 23, 2020
    Date of Patent: August 1, 2023
    Assignee: PROTON WORLD INTERNATIONAL N.V.
    Inventors: Youssef Ahssini, Guy Restiau
  • Patent number: 11709778
    Abstract: A streaming engine employed in a digital data processor specifies a fixed read only data stream defined by plural nested loops. An address generator produces address of data elements. A steam head register stores data elements next to be supplied to functional units for use as operands. The streaming engine stores an early address of next to be fetched data elements and a late address of a data element in the stream head register for each of the nested loops. The streaming engine stores an early loop counts of next to be fetched data elements and a late loop counts of a data element in the stream head register for each of the nested loops.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: July 25, 2023
    Assignee: Texas Instmments Incorporated
    Inventors: Joseph Zbiciak, Timothy D. Anderson
  • Patent number: 11704266
    Abstract: A control method and device for bidirectional communication are provided. A handshake between the master and slave communication units is realized by sending the training sequence. The master communication unit is controlled to obtain control information from the ECU. The control information is packaged into the custom package, and the custom package is encoded. The master communication unit is controlled to send the custom package to the slave communication unit. The slave communication unit decodes, verifies and corrects the custom package. The slave communication unit feeds back the correct message to the master communication unit if the custom package is verified to be correct, else feeds back the error message to the master communication unit. The master communication unit resends the custom package to the slave communication unit if it receives the error information or does not receive any feedback information within the preset time period.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: July 18, 2023
    Assignee: SHENZHEN LONTIUM SEMICONDUCTOR TECHNOLOGY CO., LTD.
    Inventors: Xinrun Xing, Shengquan Hu, Shenghui Bao, Jin Su, Lei Li
  • Patent number: 11687337
    Abstract: A method for operation of a processor core is provided. A rejected first load instruction is received that has been rejected due to a false load-hit-store detection against a first store instruction. A warning label is generated on a basis of the false load-hit-store detection. The warning label is added to the received first load instruction to create a labeled first load instruction. The labeled first load instruction is issued such that the warning label causes the labeled first load instruction to bypass the first store instruction in the store reorder queue and thereby avoid another false load-hit-store detection against the first store instruction. A computer system and a processor core configured to operate according to the method are also disclosed herein.
    Type: Grant
    Filed: August 20, 2021
    Date of Patent: June 27, 2023
    Assignee: International Business Machines Corporation
    Inventors: Bryan Lloyd, Brian Chen, Kimberly M. Fernsler
  • Patent number: 11687471
    Abstract: A method is described. The method includes executing solid state drive program code from system memory of a computing system to perform any/all of garbage collection, wear leveling and logical block address to physical block address translation routines for a solid state drive that is coupled to a computing system that the system memory is a component of.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: June 27, 2023
    Assignee: SK Hynix NAND Product Solutions Corp.
    Inventors: Joseph D. Tarango, Randal Eike, Michael Allison, Eric Hoffman
  • Patent number: 11687338
    Abstract: The technology disclosed herein provides a method including determining one or more dedicated computations storage programs (CSPs) used in a target market for a computational storage device, storing the dedicated CSPs in one or more pre-programmed computing instruction set (CIS) slots in the computational storage device, translating one or more instructions of the dedicated CSPs for processing using a native processor, loading one or more instructions of programmable CSPs to a CSP processor implemented within an application specific integrated circuit (ASIC) of the computational storage device, and processing the one or more instructions of the programmable CSPs using the CSP processor.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: June 27, 2023
    Assignee: SEAGATE TECHNOLOGY LLC
    Inventor: Marc Tim Jones
  • Patent number: 11687339
    Abstract: The present disclosure provides a data processing method and an apparatus and a related product. The products include a control module including an instruction caching unit, an instruction processing unit, and a storage queue unit. The instruction caching unit is configured to store computation instructions associated with an artificial neural network operation; the instruction processing unit is configured to parse the computation instructions to obtain a plurality of operation instructions; and the storage queue unit is configured to store an instruction queue, where the instruction queue includes a plurality of operation instructions or computation instructions to be executed in the sequence of the queue. By utilizing the above-mentioned method, the present disclosure can improve the operation efficiency of related products when performing operations of a neural network model.
    Type: Grant
    Filed: May 21, 2021
    Date of Patent: June 27, 2023
    Assignee: CAMBRICON TECHNOLOGIES CORPORATION LIMITED
    Inventors: Shaoli Liu, Bingrui Wang, Zhen Li, Jun Liang
  • Patent number: 11675599
    Abstract: An information handling system may include a processor, one or more accelerators communicatively coupled to the processor, and a management controller communicatively coupled to the processor and the one or more accelerators and configured for out-of-band management of the information handling system, the management controller further configured to receive information regarding the one or more accelerators, determine a criticality factor for each of the one or more accelerators based on the information, determine an accelerator health status for each of the one or more accelerators, and determine an overall system health of the information handling system based on the criticality factors and the accelerator health statuses.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: June 13, 2023
    Assignee: Dell Products L.P.
    Inventors: Chitrak Gupta, Rama Rao Bisa, John R. Palmer
  • Patent number: 11675590
    Abstract: Disclosed embodiments relate to systems and methods for performing instructions to transform matrices into a row-interleaved format. In one example, a processor includes fetch and decode circuitry to fetch and decode an instruction having fields to specify an opcode and locations of source and destination matrices, wherein the opcode indicates that the processor is to transform the specified source matrix into the specified destination matrix having the row-interleaved format; and execution circuitry to respond to the decoded instruction by transforming the specified source matrix into the specified RowInt-formatted destination matrix by interleaving J elements of each J-element sub-column of the specified source matrix in either row-major or column-major order into a K-wide submatrix of the specified destination matrix, the K-wide submatrix having K columns and enough rows to hold the J elements.
    Type: Grant
    Filed: July 15, 2022
    Date of Patent: June 13, 2023
    Assignee: Intel Corporation
    Inventors: Raanan Sade, Robert Valentine, Bret Toll, Christopher J. Hughes, Alexander F. Heinecke, Elmoustapha Ould-Ahmed-Vall, Mark J. Charney
  • Patent number: 11650818
    Abstract: A processor includes an execution unit and a processing logic operatively coupled to the execution unit, the processing logic to: enter a first execution state and transition to a second execution state responsive to executing a control transfer instruction. Responsive to executing a target instruction of the control transfer instruction, the processing logic further transitions to the first execution state responsive to the target instruction being a control transfer termination instruction of a mode identical to a mode of the processing logic following the execution of the control transfer instruction; and raises an execution exception responsive to the target instruction being a control transfer termination instruction of a mode different than the mode of the processing logic following the execution of the control transfer instruction.
    Type: Grant
    Filed: August 17, 2021
    Date of Patent: May 16, 2023
    Assignee: Intel Corporation
    Inventors: Vedvyas Shanbhogue, Jason W. Brandt, Ravi L. Sahita, Xiaoning Li
  • Patent number: 11652718
    Abstract: A semiconductor device and an operating method thereof are provided. An operating method of a semiconductor device, includes monitoring a plurality of request packets and a plurality of response packets that are being transmitted between a master device and a slave device; detecting a target request packet that matches desired identification (ID) information from among the plurality of request packets; counting the number of events of a transaction including the target request packet by using an event counter; counting the number of request packets whose corresponding response packets are yet to be detected, from among the plurality of request packets by using a Multiple Outstanding (MO) counter; determining whether an MO count value of the MO counter is valid; and if the MO count value is invalid, resetting the event counter.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: May 16, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jae Geun Yun, Seong Min Jo, Yun Kyo Cho, Byeong Jin Kim, Dong Soo Kang, Nak Hee Seong