Patents Examined by Hyung-Sub Sough
  • Patent number: 6232564
    Abstract: A printed circuit board having a signal plane with increased channel width for enhanced wireability. The printed circuit board has a top plane having component lands arranged in a grid, wherein the component lands include a first grouping arranged in a first diagonal, and a second grouping arranged in a second diagonal where the second diagonal is parallel and adjacent to the first diagonal, a plurality of offset lands placed within the first diagonal between the component lands therein, and a plurality of electrical connectors electrically coupling component lands in the second diagonal to adjacent offset lands in the first diagonal.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: May 15, 2001
    Assignee: International Business Machines Corporation
    Inventors: Steven Frederick Arndt, Mark Budman, James Richard Stack
  • Patent number: 6229101
    Abstract: A substrate for mounting an electronic part and a method for producing the same, which allows a conductive pin to be inserted and secured in a through hole without exerting any damage thereto. The substrate for mounting an electronic part is formed of a through hole piercing an insulating substrate and a conductive pin with its head inserted into the through hole. The head of the conductive pin is provided with a plurality of projections to its side wall, each projecting radially in 4 or more directions. Those projections form a plurality of pairs, each of which is extending in an opposite direction from an axial center of the head. Those projection pairs include a primary projection pair having a largest length and a secondary projection pair having a second largest length. The length of the primary projection pair is equal to or more than an inside diameter of the through hole. The length of the secondary projection pair is less than the inside diameter of the through hole.
    Type: Grant
    Filed: June 10, 1999
    Date of Patent: May 8, 2001
    Assignee: Ibiden Co. Ltd.
    Inventors: Masataka Sekiya, Tsunehisa Takahashi, Akihiro Demura, Takuji Asai
  • Patent number: 6229097
    Abstract: A substrate 15 has an electrically adjustable trim pad 50 on the bottom side. A circuit pattern 18 resides on the top side, covered by an RF shield 20. The trim pad is located on the bottom side directly below the RF shield, and is electrically connected 52 to the circuit pattern. A number of surface mount connections 30, typically C5 solder bumps, are located on the bottom side, and surround the trim pad. The trim pad is trimmed after the RF shield is attached, thus providing more accurate tuning of the circuit on the top side.
    Type: Grant
    Filed: March 8, 1996
    Date of Patent: May 8, 2001
    Assignee: Motorola, Inc.
    Inventors: Anthony J. Suppelsa, Richard J. Kolcz, Carl M. Thielk, Branko Avanic
  • Patent number: 6222135
    Abstract: A circuit board (10) on which surface electronic components (15) are mounted during a reflow process comprises a circuit portion (12), a surrounding circumferential portion (13) and at least one elongated opening (14) formed in the surrounding circumferential portion substantially parallel to the direction the board travels during the reflow direction (16) to prevent electronic component soldering failures that may occur as a result of the deflection of the circuit board flow process.
    Type: Grant
    Filed: October 21, 1998
    Date of Patent: April 24, 2001
    Assignee: International Business Machines Corporation
    Inventors: Yukiko Daido, Yoshihisa Hatta
  • Patent number: 6222740
    Abstract: A multilayer circuit board includes multiple conductor path planes arranged one above another and separated by insulating material layers. The multilayer circuit board includes at least one electronic component (in particular an LCCC) placed on one of the two outer sides of the multilayer circuit board. The multilayer circuit board includes at least one core substrate arranged in the multilayer circuit board between the outer insulating material layers. The core substrate largely adapts the thermal expansion properties of the multilayer circuit board, at least in the coverage area of the electronic component, to the thermal expansion properties of the component. In order to achieve a reduction in the weight of the multilayer circuit board, an inner layer portion, equipped with a recess, is provided between the two outer insulating material layers.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: April 24, 2001
    Assignee: Robert Bosch GmbH
    Inventors: Kurt Bovensiepen, Helmut Ulmer, Gerhard Messarosch
  • Patent number: 6218628
    Abstract: A method for the manufacture of printed circuit boards, foil circuit boards and semifinished products for printed and foil circuit boards formed from preliminary products with electrically conductive coatings (7, 8) structurable to conductor patterns and structurable substrates (4), for the formation of connectors (V), contours (K) and conductor patterns (L), the connectors (V), contours (K) and conductor patterns (L) being structured simultaneously or in the same method steps from the preliminary products, and the connectors (V) and contours (K) are part of the structured preliminary product substrate, the connectors (V) being brought for electrical or mechanical connection into a position in which they are connectable and the finished conductor patterns (L) can be separated at contours (K).
    Type: Grant
    Filed: January 18, 1996
    Date of Patent: April 17, 2001
    Assignee: Dyconex Patente AG
    Inventors: Walter Schmidt, Marco Martinelli
  • Patent number: 6215072
    Abstract: Provided is an oxide superconducting conductor consisting of a plurality of metal-covered multifilamentary superconducting wires which are assembled with each other. Bending is applied to the superconducting conductor for improving its critical current density. It is possible to obtain a compact superconducting conductor having higher capacity, since its critical current density is increased by such application of bending.
    Type: Grant
    Filed: October 19, 1994
    Date of Patent: April 10, 2001
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Jun Fujikami, Nobuhiro Shibuta, Kenichi Sato, Tsukushi Hara, Hideo Ishii
  • Patent number: 6215068
    Abstract: A line guiding assembly is provided having lines that are held together by a common line bundling apparatus. The line bundling apparatus has disposed on its outside a sliding apparatus which acts in the longitudinal direction of the lines. The sliding apparatus prevents friction between an upper length portion and a lower length portion of a line assembly.
    Type: Grant
    Filed: August 13, 1997
    Date of Patent: April 10, 2001
    Assignee: Kabelschlepp GmbH
    Inventor: Karl Meier
  • Patent number: 6215076
    Abstract: Noise frequency generated from a circuit is determined. The distance between two arbitrary lines of a plurality of power feed lines or a plurality of power return lines extending parallel to each other is determined on the basis of the determined noise frequency in question. The distance between jumper lines for bridging the two arbitrary lines is determined on the basis of the noise frequency, thereby suppressing emitted noise which can be generated on a printed circuit board.
    Type: Grant
    Filed: March 26, 1997
    Date of Patent: April 10, 2001
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hideho Inagawa, Toru Otaki
  • Patent number: 6211469
    Abstract: A printed-circuit substrate is described. A film-shaped support base having an electrical insulating property and elasticity is provided with a resin mold section for supporting an integrated circuit. A plurality of foil-shaped electric conductors are connected to the integrated circuit at their base side and are supported by the support base so as to extend toward the periphery of the support base at their tip side. The conductors are formed on a first surface of the support base and the first base faces electrodes of an external device. Exposed portions are provided by removing the support base in an intersecting direction of the foil-shaped electric conductors over an entire area of the support base between the integrated circuit and the periphery thereof, so that one portion of each foil-shaped electric conductor is exposed by separating the main support base supporting the integrated circuit and the periphery thereof.
    Type: Grant
    Filed: December 18, 1997
    Date of Patent: April 3, 2001
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Toshimichi Taguchi
  • Patent number: 6207905
    Abstract: In the glass-ceramic composition, a weight ratio of a glass and a ceramic is 40 to 60:60 to 40. The glass is composed of 40 to 60 wt % of SiO2, 5 to 9 wt % of Al2O3, 1 to 10 wt % of B2O3, 3 to 5 wt % of Na2O+K2O, 3 to 15 wt % of CaO+MgO+ZnO, and 15 to 40 wt % of PbO, and does not contain Li2O. A softening point of the glass is 650 to 780° C. The circuit substrate includes a laminate substrate formed by laminating insulating substrates, and a conductor circuit formed on a surface of each insulating substrate. The insulating substrate is formed of the glass-ceramic composition. A wiring layer and a via hole conductor are provided inside the laminate substrate.
    Type: Grant
    Filed: August 2, 1999
    Date of Patent: March 27, 2001
    Assignee: NGK Spark Plug Co., Ltd.
    Inventors: Shigeru Taga, Hiroyuki Takahashi, Yoshitaka Yoshida
  • Patent number: 6207903
    Abstract: Structures and methods that provide for via transitions between opposite sides of a high resistivity silicon micro-machined membrane substrate. The via transitions provide ground-signal-ground interconnection between coplanar waveguides disposed on opposite sides of substrate. Adjacent via transitions are anisotropically etched from opposite surfaces of the substrate to form the via transitions. The ground-signal-ground configuration provides RF impedance matching at the via transition.
    Type: Grant
    Filed: December 10, 1998
    Date of Patent: March 27, 2001
    Assignee: Raytheon Company
    Inventors: Cheng P. Wen, Linda P. B. Katehi, Stephen Robertson, Thomas Ellis, Katherine Herrick, Gabriel M. Rebeiz
  • Patent number: 6207906
    Abstract: A printed circuit board (PCB) for mounting a dielectric radio frequency (RF) band pass filter (BPF) thereon, and a method of making the same, is provided. The filter has an input terminal, an output terminal, and a ground terminal including a first, a second, and a third terminal. The PCB includes a first terminal for mounting the input terminal of the RF BPF thereon. A second terminal of the PCB is for mounting the output terminal of the RF BPF thereon. The second terminal is disposed horizontally apart from said first terminal by a predetermined distance. A third terminal of the PCB is for mounting the first terminal of the ground terminal of the RF BPF thereon. The third terminal is disposed between said first and said second terminals. A fourth terminal of the PCB is for mounting the second terminal of the ground terminal of the RF BPF thereon. The fourth terminal is disposed vertically apart from said first terminal by a predetermined distance.
    Type: Grant
    Filed: November 4, 1998
    Date of Patent: March 27, 2001
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ju-Nyun Kim
  • Patent number: 6204453
    Abstract: A method of forming a printed circuit board or circuit card is provided with a metal layer which serves as a power plane sandwiched between a pair of photoimageable dielectric layers. Photoformed metal filled vias and photoformed plated through holes are in the photopatternable material, and signal circuitry is on the surfaces of each of the dielectric materials and connected to the vias and plated through holes. A border may be around the board or card including a metal layer terminating in from the edge of one of the dielectric layers. A copper foil is provided with clearance holes. First and second layers of photoimageable curable dielectric material is disposed on opposite sides of the copper which are photoimageable material. The patterns are developed on the first and second layers of the photoimageable material to reveal the metal layer through vias. At the clearance holes in the copper, through holes are developed where holes were patterned in both dielectric layers.
    Type: Grant
    Filed: December 2, 1998
    Date of Patent: March 20, 2001
    Assignee: International Business Machines Corporation
    Inventors: Kenneth Fallon, Miguel A. Jimarez, Ross W. Keesler, John M. Lauffer, Roy H. Magnuson, Voya R. Markovich, Irv Memis, Jim P. Paoletti, Marybeth Perrino, John A. Welsh, William E. Wilson
  • Patent number: 6205345
    Abstract: In order to obtain a superconducting wire containing an oxide superconductor, whose critical current density is not much reduced upon application of bending, a plurality of strands 3, comprising oxide superconductors 1 covered with first metal sheaths 2, are filled into a second metal sheath 4, and deformation processing is performed to sectionally apply a compressive load to the second metal sheath, so that the thickness of the oxide superconductor 1 contained in each strand 3 is not more than 5% of the overall thickness of the superconducting wire 6.
    Type: Grant
    Filed: November 13, 1996
    Date of Patent: March 20, 2001
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Kenichi Sato, Hidehito Mukai, Nobuhiro Shibuta
  • Patent number: 6199266
    Abstract: A superconductor cable with high interstrand resistance is produced from superconductor wire strands which has been electroplated with nickel. The wire strands have filaments of a superconductor alloy in a normally conducting metal matrix and are electroplated before they are formed into an elongated bundle of generally circular cross section. This bundle is then deformed and compacted into a superconductor cable of generally polygonal cross section which is usually trapezoidal. The superconductor wire is preferably comprised of a multiplicity of filaments of niobium/titanium superconductor alloy disposed within a matrix of copper.
    Type: Grant
    Filed: April 11, 1994
    Date of Patent: March 13, 2001
    Assignee: New England Electric Wire Corporation
    Inventor: Robert F. Meserve
  • Patent number: 6198051
    Abstract: Disclosed is a transparent substrate element for electronic displays that includes a transparent base layer, a plurality of independently addressable transparent electrodes disposed on the base layer, and a contiguous metallic coating associated with each transparent conductive electrode to increase the conductivity of the associated transparent conductive electrode, wherein the contiguous metallic coating comprises a periodic array of holes arranged to allow a significant amount of visible light to be transmitted through the substrate element.
    Type: Grant
    Filed: October 22, 1999
    Date of Patent: March 6, 2001
    Assignee: 3M Innovative Properties Company
    Inventors: Robert S. Moshrefzadeh, Raghunath Padiyath
  • Patent number: 6194665
    Abstract: A plastic film distinguished in corona resistant characteristic having a low cost without a low mechanical strength, which plastic film is particularly suitable for making insulated wires, coils, and electric motors capable of fully responding to demands for providing electric trains with higher running speeds and higher acceleration and deceleration. In accordance with one embodiment, the film includes a base layer and at least one thermally conductive layer having a minimum thermal conductivity of 2 W/m·K, preferably 6 W/m·K, more preferably 15 W/m·K laminated horizontally on at least one surface of the base layer. In accordance with another embodiment, the film has a minimum volume electrical resistivity of 1014 &OHgr;·cm, preferably 1015 &OHgr;·cm, and includes a base layer and at least one low-electrical-resistance layer having a maximum superficial electrical resistance of 1013 &OHgr;·cm, preferably 1012 &OHgr;·CM.
    Type: Grant
    Filed: October 25, 1996
    Date of Patent: February 27, 2001
    Assignee: Kanegafuchi Kagaku Kogyo Kabushiki
    Inventors: Eiichirou Kuribayashi, Keigo Nishida, Yoshihide Ohnari
  • Patent number: 6175509
    Abstract: The present invention is a mounting platform for placement of a first device on a first plane in close proximity to a second device on a second plane. In the preferred embodiment, the first device is a voltage regulator circuit, the second device is a microprocessor, the first plane is the surface of the platform printed circuit board (PCB), and the second plane is the surface of the base printed circuit board. Typically the microprocessor is electrically coupled to the base printed circuit board and the voltage regulator circuit is electrically coupled to the platform printed circuit board. The mounting platform is mounted as a mezzanine over the base printed circuit board on the platform printed circuit board. Mounting the voltage regulator in this way allows the voltage regulator output to be placed adjacent to the microprocessor chip while at the same time minimizing the amount of valuable board space that is used.
    Type: Grant
    Filed: May 14, 1997
    Date of Patent: January 16, 2001
    Assignee: Hewlett-Packard Company
    Inventor: James K. Koch
  • Patent number: 6175084
    Abstract: A metal-base multilayer circuit substrate has a metal plate and a circuit substrate bonded to the metal plate, by an insulating adhesive layer containing at least one of metal oxides and/or at least one of metal nitrides. The adhesive layer has high heat conductivity and allows for a metal-base multilayer circuit substrate having excellent heat dissipating properties.
    Type: Grant
    Filed: April 8, 1996
    Date of Patent: January 16, 2001
    Assignee: Denki Kagaku Kogyo Kabushiki Kaisha
    Inventors: Toshiki Saitoh, Naomi Yonemura, Tomohiro Miyakoshi, Makoto Fukuda