Abstract: An electronic apparatus includes a window, a display module that includes a module hole, an optical member disposed between the window and the display module and in which a first opening that overlaps the module hole is formed, and a cover pattern disposed on an inner surface of the first opening of the optical member.
Abstract: Disclosed herein are IC structures, packages, and devices that include III-N transistor arrangements that may reduce nonlinearity of off-state capacitance of the III-N transistors. In various aspects, III-N transistor arrangements limit the extent of access regions of the transistors, compared to conventional implementations, which may limit the depletion of the access regions. Due to the limited extent of the depletion regions of a transistor, the off-state capacitance may exhibit less variability in values across different gate-source voltages and, hence, exhibit a more linear behavior during operation.
Type:
Grant
Filed:
May 22, 2019
Date of Patent:
July 2, 2024
Assignee:
Intel Corporation
Inventors:
Nidhi Nidhi, Han Wui Then, Marko Radosavljevic, Sansaptak Dasgupta, Paul B. Fischer, Rahul Ramaswamy, Walid M. Hafez, Johann Christian Rode
Abstract: Provided is a display device. The display device includes a substrate, a light emitting diode that is disposed on the substrate, and includes a pixel electrode, a common electrode, and an emission layer disposed between the pixel electrode and the common electrode; an encapsulation layer that is disposed on the light emitting diode, a touch electrode that is disposed on the encapsulation layer, a light blocking portion that is disposed on the touch electrode, a color filter layer that overlaps the emission layer, and a planarization layer that is disposed on the light blocking portion and the color filter layer, wherein the color filter layer is disposed on the encapsulation layer and the light blocking portion, and an edge portion of the color filter layer overlaps the light blocking portion.
Type:
Grant
Filed:
April 13, 2021
Date of Patent:
July 2, 2024
Assignee:
Samsung Display Co., Ltd.
Inventors:
Nak Cho Choi, Baek Min Oh, Eon Joo Lee, Hae Young Yun
Abstract: A display device includes: a substrate; a display layer arranged above the substrate and including a display element; an encapsulation layer above the display layer; a lower light-shielding layer above the encapsulation layer; an upper light-shielding layer at least partially overlapping the lower light-shielding layer in a plan view and arranged above the lower light-shielding layer; and an organic layer arranged between the lower light-shielding layer and the upper light-shielding layer and separating the lower light-shielding layer and the upper light-shielding layer from each other.
Type:
Grant
Filed:
July 21, 2021
Date of Patent:
June 25, 2024
Assignee:
SAMSUNG DISPLAY CO., LTD.
Inventors:
Hyunduck Cho, Sungmin Kim, Hongjo Park, Chiwook An
Abstract: A display substrate, a method of forming a display substrate, a display panel and a display device are provided. The display substrate includes a thin film transistor array layer, where a semiconductor material layer pattern of a driving transistor in the thin film transistor array layer includes a first channel portion, and the first channel portion includes a first sub-channel portion and a second sub-channel portion; the semiconductor material layer pattern further includes a first conductive portion, an included angle between a straight line where a current conduction direction of the first sub-channel portion is located and a straight line where an extending direction of a data line in the thin film transistor array layer is located is a first included angle.
Abstract: A light emitting diode (LED) stack for a display including a first LED stack including a first conductivity-type semiconductor layer and a second conductivity-type semiconductor layer, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, an intermediate bonding layer disposed between the first LED stack and the second LED stack to bond the second LED stack to the first LED stack, an upper bonding layer disposed between the second LED stack and the third LED stack to couple the third LED stack to the second LED stack, and a first hydrophilic material layer disposed between the first LED stack and the upper bonding layer.
Type:
Grant
Filed:
November 4, 2021
Date of Patent:
June 25, 2024
Assignee:
SEOUL VIOSYS CO., LTD.
Inventors:
Jong Hyeon Chae, Seong Gyu Jang, Ho Joon Lee, Chang Yeon Kim, Chung Hoon Lee
Abstract: In one example, a semiconductor device includes a substrate having a top side and a conductor on the top side of the substrate, an electronic device on the top side of the substrate connected to the conductor on the top side of the substrate via an internal interconnect, a lid covering a top side of the electronic device, and a thermal material between the top side of the electronic device and the lid, wherein the lid has a through-hole. Other examples and related methods are also disclosed herein.
Abstract: A display device having a thin-film transistor with increased mobility of electrons or holes includes a first semiconductor layer arranged on a substrate and including a first channel region, a first source region, and a first drain region; a first stressor arranged between the substrate and the first semiconductor layer and which overlaps the first source region in a plan view; a second stressor arranged between the substrate and the first semiconductor layer and which overlaps the first drain region in the plan view, where the second stressor is spaced apart from the first stressor; a gate insulating layer arranged on the first semiconductor layer; and a first gate electrode arranged on the gate insulating layer and which overlaps the first semiconductor layer in the plan view.
Type:
Grant
Filed:
January 4, 2021
Date of Patent:
June 18, 2024
Assignee:
SAMSUNG DISPLAY CO., LTD.
Inventors:
Junehwan Kim, Taeyoung Kim, Jongwoo Park, Kiju Im, Hyuncheol Hwang
Abstract: When a value obtained by dividing the number of the one or more second regions by a total of the number of the one or more first regions and the number of the one or more second regions is defined as a first defect free area ratio, a value obtained by dividing the number of the one or more fourth regions by a total of the number of the one or more third regions and the number of the one or more fourth regions is defined as a second defect free area ratio, and a value obtained by dividing the number of the one or more macroscopic defects by an area of the central region is defined as X cm?2, A is smaller than B, B is less than or equal to 4, X is more than 0 and less than 4, and a Formula 1 is satisfied.
Type:
Grant
Filed:
June 14, 2019
Date of Patent:
June 18, 2024
Assignee:
Sumitomo Electric Industries, Ltd.
Inventors:
Kenji Kanbara, Hironori Itoh, Tsutomu Hori
Abstract: A display device includes: a display panel having a front portion, a first bending portion, a second bending portion, and a corner portion, the display panel including a plurality of first pixels disposed in the front portion and a plurality of second pixels disposed in the corner portion. The display panel includes: a substrate; a first dam surrounding the plurality of first pixels; and a second dam surrounding the plurality of second pixels. The substrate includes a plurality of cutout patterns disposed in the corner portion, the plurality of second pixels and the second dam are disposed in each of the plurality of cutout patterns, and a height of an upper surface of the first dam is higher than a height of an upper surface of the second dam, based on one surface of the substrate.
Type:
Grant
Filed:
September 23, 2021
Date of Patent:
June 18, 2024
Assignee:
SAMSUNG DISPLAY CO., LTD.
Inventors:
Hye Min Lee, Hyoung Sub Lee, Jin Ho Hyun, Woo Yong Sung
Abstract: A light emitting diode (LED) stack for a display including a substrate, a first LED stack disposed on the substrate, a second LED stack disposed on the first LED stack, a third LED stack disposed on the second LED stack, a first color filter interposed between the first LED stack and the second LED stack, and a second color filter interposed between the second LED stack and the third LED stack, in which the second LED stack and the third LED stack are configured to transmit light generated from the first LED stack to the outside, and the third LED stack is configured to transmit light generated from the second LED stack to the outside.
Type:
Grant
Filed:
July 2, 2021
Date of Patent:
June 11, 2024
Assignee:
SEOUL VIOSYS CO., LTD.
Inventors:
Jong Hyeon Chae, Chung Hoon Lee, Seong Gyu Jang, Chang Yeon Kim, Ho Joon Lee
Abstract: Provided is a display device capable of displaying a high-quality image even under high temperature conditions, the display device including a flexible substrate, a pixel circuit layer arranged on the flexible substrate, and including a thin-film transistor and a through hole extending to the flexible substrate, a first organic layer arranged on the pixel circuit layer and in contact with the flexible substrate through the through hole, an inorganic layer arranged on the first organic layer to cover an upper surface of the first organic layer, a pixel electrode arranged on the inorganic layer, and an encapsulation layer arranged on the pixel electrode, and including a first inorganic encapsulation layer, a second inorganic encapsulation layer, and an organic encapsulation layer between the first inorganic encapsulation layer and the second inorganic encapsulation layer.
Type:
Grant
Filed:
August 1, 2019
Date of Patent:
June 11, 2024
Assignee:
Samsung Display Co., Ltd.
Inventors:
Jongho Hong, Sangwoo Kim, Jaemin Shin, Junhyeong Park
Abstract: An electronic apparatus includes a window, a display module that includes a module hole, an optical member disposed between the window and the display module and in which a first opening that overlaps the module hole is formed, and a cover pattern disposed on an inner surface of the first opening of the optical member.
Abstract: A display device includes a light emitting structure disposed on a substrate, and a thin film encapsulation layer disposed on the light emitting structure and including an inorganic layer containing silicon oxynitride and an organic layer. A portion of the inorganic layer has a stress intensity factor of about 1.6 MPa or more.
Type:
Grant
Filed:
August 19, 2021
Date of Patent:
June 4, 2024
Assignee:
SAMSUNG DISPLAY CO., LTD.
Inventors:
Juwon Lee, Ojun Kwon, Ran Kim, Soonmi Choi
Abstract: A display device includes a camera see-through area which includes a camera module disposed therein; a routing area which is disposed in the vicinity of the camera see-through area and is bypassed by at least one data line and scan line; and a pixel area which includes the camera see-through area and the routing area and includes a plurality of sub-pixels including an organic light emitting diode and a cathode disposed therein.
Type:
Grant
Filed:
December 17, 2020
Date of Patent:
June 4, 2024
Assignee:
LG DISPLAY CO., LTD.
Inventors:
DongJun Kim, JiChul Lim, SungWook Yoon, KwangMin Hyun
Abstract: A display device includes a substrate including a first region, a second region, and a bending region between the first region and the second region, a protective substrate disposed below the substrate in the first region, the second region, and the bending region, a cushion layer disposed below the protective substrate in the first region and the second region, a pixel layer disposed on the substrate in the second region, and a drive chip disposed on the substrate in the first region. The substrate is bent at the bending region such that the first region overlaps the second region.
Abstract: A display apparatus includes a display panel having a display substrate on which a plurality of pad terminals is disposed, and a driving unit having a plurality of driving terminals electrically connected to the plurality of pad terminals. Each of the plurality of pad terminals includes a stepped groove that faces a corresponding driving terminal of the plurality of driving terminals or each of the plurality of pad terminals includes an opening hole that faces the corresponding driving terminal of the plurality of driving terminals.
Type:
Grant
Filed:
January 31, 2023
Date of Patent:
May 28, 2024
Assignee:
SAMSUNG DISPLAY CO., LTD.
Inventors:
Byoungyong Kim, Seunghwa Ha, Seungsoo Ryu, Sanghyeon Song, Jeongdo Yang, Jungyun Jo, Jeongho Hwang
Abstract: A display device is provided. The display device includes a cover plate, a first adhesive layer, a glass layer, a second adhesive layer, and a buffer layer. The first adhesive layer, the glass layer, and the second adhesive layer are sequentially disposed on a side of the cover plate. The glass layer is made of reinforced ultra-thin glass. Peripheral edges of the glass layer are indented with respect to peripheral edges of the first adhesive layer and the second adhesive layer to form an indented region. The buffer layer is disposed in the indented region.
Type:
Grant
Filed:
March 17, 2021
Date of Patent:
May 28, 2024
Assignee:
WUHAN CHINA STAR OPTOELECTRONICS SEMICONDUCTOR DISPLAY TECHNOLOGY CO., LTD.
Abstract: A light emission element of an embodiment of the present disclosure includes at least: a base; a recessed portion provided at a surface of the base; a first electrode layer formed at least partially along a shape of a top surface of the recessed portion; an organic layer formed on the first electrode layer at least partially along a shape of a top surface of the first electrode layer; a second electrode layer formed on the organic layer along a shape of a top surface of the organic layer; and a planarization layer formed on the second electrode layer, in which light from the organic layer is emitted to an outside via the second electrode layer and the planarization layer.
Type:
Grant
Filed:
October 20, 2022
Date of Patent:
May 28, 2024
Assignee:
Sony Semiconductor Solutions Corporation
Abstract: Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.
Type:
Grant
Filed:
June 26, 2020
Date of Patent:
May 28, 2024
Assignee:
Intel Corporation
Inventors:
Cheng-Ying Huang, Gilbert Dewey, Anh Phan, Nicole K. Thomas, Urusa Alaan, Seung Hoon Sung, Christopher M. Neumann, Willy Rachmady, Patrick Morrow, Hui Jae Yoo, Richard E. Schenker, Marko Radosavljevic, Jack T. Kavalieros, Ehren Mannebach