Abstract: A process for fabricating high density, high voltage CMOS devices. The process provides self-aligning, full channel stops which are formed prior to the fabrication of the active devices. The aligned full channel stops and a well are formed in the substrate without intermediate masking.

Abstract: The field inversion properties of integrated circuits incorporating N-channel MOS devices are improved by using a silicon substrate whose bulk dopant concentration is low, but whose local dopant concentration is high at the field surfaces under the field oxide separating the active surface areas where the individual N-channel MOS devices are formed. The differential doping between surface areas under the field oxide and the active surface areas of the substrate is done by nonselectively ion-implanting boron into the substrate to form a uniform low resistivity layer, removing selected portions of the low resistivity layer to expose the unimplanted, high resistivity substrate and forming the active devices at the unimplanted substrate portions. As an option, the unimplanted surface portion can be doped to an intermediate dopant concentration to improve performance. The remaining pattern of the low resistivity layer is covered with field oxide.

Abstract: A circular semiconductor wafer includes a thyristor surrounded by a diode through an annular V-shaped groove-filled with glass. That face of the wafer near to the extremity of the groove is disposed on a molybdenum plate through a brazing layer. A base layer on both faces of the wafer has those portions extending through the associated emitter region at predetermined positions to be exposed to the wafers face to form degenerate P-N junctions on and adjacent that face with the adjacent emitter portions. The brazing layer and the opposite electrode for the thyristor include small openings looking the exposed portions of the base layers and the adjacent emitter portions respectively.

Abstract: The body of a PIN photodiode is of a silicon semiconductor material. The PIN photodiode has a large area incident surface on which light impinges and is operated at high voltages. In the fabrication of a PIN photodiode, as described, a high concentration of N-type dopant is deposited on the body. It has been discovered that if a phosphorus silicate glass, as a source of N-type dopant, is in contact with a surface of the PIN photodiode body in a high temperature ambient and for an extended period of time, lattice damage on the surface of the silicon body results. These lattice defects are responsible for premature voltage breakdown in the device. In a first method of fabrication of PIN photodiode devices the phosphorus silicate glass is on the silicon surface for about 12 minutes after which it is removed and then any phosphorus atoms in the surface of the body are diffused into the body.

Abstract: A method of manufacturing a semiconductor device, in which on a basic mask of a first material there is provided a layer of a second material, after which the first material with the second material present thereon is removed, and an island of the second material remaining with a window of the basic mask is used as an alignment feature for a subsequent mask.

Abstract: In a first step, the semiconductor material is doped in a known manner with impurities having a given conductivity type and a given concentration profile. In a second step, the material is maintained at a high temperature, bombarded with a beam of particles which are accelerated with a given energy so as to penetrate into the crystal during a predetermined time interval. The resultant migration of impurities produces an increase in the impurity concentration irrespective of the sign of the initial concentration gradient within a zone adjacent to the zone of stopping of the particles.

Abstract: PN junctions in mercury cadmium telluride are formed by implantation of gold ions and a subsequent low temperature--short duration heat treatment.

Abstract: A process for producing complementary metal-oxide-semiconductor/silicon-on-sapphire (CMOS/SOS) devices wherein undesirable effects of phosphorous on sapphire are avoided.

Abstract: A method of depositing a layer comprising SiO.sub.2 on a surface of a substrate at a rate which is temperature independent is disclosed. The method includes combining dichlorosilane (SiH.sub.2 Cl.sub.2) with an oxidizing gas, such as O.sub.2, CO.sub.2, N.sub.2 O, H.sub.2 O, to form SiO.sub.2.

Abstract: An MOS bucket brigade delay line having reduced parasitic capacitances and method for making the same, include a first set of diffused drain source regions in a semiconductor substrate, a thin gate oxide layer overlying said diffused regions, a plurality of gate electrodes having first and second edges, the first edge of each electrode substantially overlapping one of said diffused regions, each of these elements formed in conventional manner. A second set of diffused drain-source regions extends the first set of regions by an amount limited by the second edge of the gate electrodes. The second set of drain source regions is formed by utilizing the gate electrodes as a diffusion mask.

Abstract: Method for forming metal oxide semiconductor structure with a precisely controlled channel formed by a combination of diffusion and implantation through a common mask.

Abstract: A method of forming dielectrically isolated islands of semiconductor material on which discrete devices may be formed is disclosed. A wafer of semiconductive material is provided with an oxide layer and, by ion implantation, is lightly doped after which, openings are formed in the oxide. The portions of wafer exposed by the openings are then heavily doped and the wafer is then subjected to a high temperature step to drive in the dopants and produce isolated areas.

Abstract: It has been discovered for the practice of this disclosure that a particular ion radiation treatment of amorphous SiO.sub.2 thin film, with a subsequent annealing procedure, improves the dielectric breakdown property of the film. The treated SiO.sub.2 film is found to be substantially more dense than a comparable untreated SiO.sub.2 film. It is theorized for the practice of this disclosure that the physical mechanism which produces the densification of the SiO.sub.2 film may be responsible for the enhanced dielectric properties of the film. Such an improved film is especially useful as the gate insulator layer in an insulated-gate electrode field-effect transistor device, and as an insulating layer for electrically separating two metallic films in a thin film integrated circuit. Such SiO.sub.2 thin films are useful in integrated circuit technology because the electrical insulation property thereof is considerably improved, e.g.

Abstract: Submicron plasma trimming of a patterened resist material is combined with ion implantation techniques to achieve submicron control of lateral doping profiles. This makes possible the high-yield fabrication of, for example, bipolar microwave transitors of the self-aligned-emitter type. The basic technique can also be supplied to the fabrication of high performance insulted-gate field-effect transistors, junction-gate field-effect transistors and Schottky-barrier field-effect transistors.

Abstract: Described are procedures for fabricating silicon devices which prevent the formation and/or activation of stacking fault nucleation sites during high temperature processing steps, such as steam oxidation of silicon wafers. The procedures, which take place before such high temperature steps, include forming on the back surface of the wafer a stressed layer and then annealing the wafer for a time and at a temperature effective to cause the nucleation sites to diffuse to a localized region near to the back surface. Illustratively the stressed layer comprises silicon nitride or aluminum oxide. Enhanced gettering is achieved if, prior to forming the stressed layer, interfacial misfit dislocations are introduced into the back surface by, for example, diffusion of phosphorus therein. Following the gettering step(s) on the back surface, conventional procedures, such as growing epilayers and/or forming p-n junctions, are performed on the front surface of the wafer.

Abstract: A method of manufacturing a semiconductor device, comprising the steps of providing a semiconductor body comprising a first surface and an underlying semiconductor portion that is of first conductivity type, providing a doping material of said first conductivity type at a first portion of said first surface prior to the formation of a sunken insulating layer, said first portion being situated beside said sunken insulation layer, forming an insulation layer consisting of insulating material and sunk locally in said body from said first surface, and then introducing said doping material into said semiconductor body via said first portion of said first surface so as to form a zone of said first conductivity type, said zone contacting said underlying semiconductor portion, and zone extending at the area of contact to a depth greater than that of said sunken insulation layer.

Abstract: A semiconductor wafer is electrostatically clamped against a support by positioning an intermediate solid dielectric layer therebetween and applying a potential difference, thereby firmly and evenly clamping the wafer for photoresist or ion beam implantation operations.

Abstract: A method of manufacturing semiconductor devices is disclosed which includes the steps of forming an insulating film on one surface of a semiconductor substrate, removing the insulating film selectively to expose at least a portion of one surface of the semiconductor substrate, forming a low temperature oxide film containing a first diffusion source which has a higher etch rate than the insulating film onto at least a part of the exposed surface while leaving the rest of the surface exposed, and heating the substrate to diffuse the first diffusion source film from the oxide film into the substrate and to diffuse a second diffusion source through the exposed surface into the substrate thereby at least two diffused regions can be formed on the substrate without relative displacement.

Abstract: An n channel MOSFET transistor which includes doping of previously formed source and drain elements with a heavy diffusion of phosphorous or arsenic creating n.sup.+.sup.+ regions in the source and drain. The extra diffusion step is preferably accomplished just prior to contact metalization.

Abstract: A low resistivity anode region is formed relative to the much higher resistivity gate region in a planar semiconductor controlled rectifier (SCR) structure. The low resistivity anode region is achieved by diffusing an appropriate impurity in high concentration in a distinct diffusion step separate from the diffusion of the like conductivity type gate region. The result is a desirable optimization of certain device parameters, viz., r.sub.on and V.sub.f.