Abstract: A method of setting the lifetime of charge carriers in a semiconductor body by the formation of recombination centers in the semiconductor body. The quantity of the recombination centers forming material necessary to provide the desired concentration in the semiconductor body is applied to the surface of the semiconductor body and into the surface thereof by ion implantation, and thereafter, in order to diffuse the material into the semiconductor body, the body is heated until an approximately stationary value for the charge carrier lifetime has developed in the entire volume of the body.

Abstract: Complementary semiconductor devices are fabricated in single crystal semiconductor segments within a monolithic substrate, using planar diffusion techniques. An impurity element of one conductivity-determining type is partially diffused into one of a pair of the single crystal segments having opposite conductivity types to one another. Thereafter, a second impurity element of the other conductivity-determining type and having a faster diffusion coefficient than the first element is diffused into the second of the pair of single crystal segments at a time and for a temperature sufficient to effect penetration of both impurities to substantially the same depth in their respective segments. The concentrations of the impurities are selected to provide common operational element regions of the complementary devices with substantially identical resistivities.

Abstract: A method of manufacturing a semiconductor device by means of doping via a mask. According to the invention a mask is used which is manufactured by providing one or more "first" apertures in a masking layer, after which islands of an isotropically growing material are grown in the said apertures, after which the parts of the masking layer present between the islands are removed and finally the said islands themselves are removed.

Abstract: A photon sensing device utilizing a III-V negative electron affinity photthode grown on a window substrate support which simultaneously serves as a support and growth surface for the epitaxial growth of suitable cathode layers as well as the input window for the device.

Abstract: This disclosure is directed to an ion-implanted self-aligned transistor device including the fabrication method therefor wherein the emitter region and a pair of heavily doped base contact regions are spaced in a self-aligned manner from the periphery of the emitter region in order to precisely align the base contact regions at a predetermined distance from the periphery of the emitter region. Silicon nitride and silicon dioxide insulating layers are used together with an undercutting etching operation to precisely align the pair of spaced heavily doped base contact regions with respect to the periphery of the emitter region. The final completed semiconductor structure utilizes a single base metal contact electrode which makes contact to all of the spaced heavily doped base contact regions. A single emitter metal contact electrode is provided to the emitter regions located outside the periphery of the inner spaced heavily doped base contact regions.

Abstract: A mask for use in production of semiconductor arrangements comprises a mask element with projections thereon at a side adapted to face the semiconductor arrangement, the projections being adapted to cooperate with recesses in the semiconductor arrangement to locate the mask element thereon.The invention also includes a method of producing the semiconductor arrangements.

Abstract: An Automatic End Station arrangement for use in conjunction with ion implantation apparatus to provide continuous implantation of semi-conductor wafers is disclosed. Wafers are indexed one by one out of a standard cartridge onto a conveyor track from which they are directed into the slot of a downwardly directed slotted passageway which has been defined between two appropriately sealed plate members. The wafer slides down the passageway until it is situated adjacent to a portion of the passageway in communication with an ion implantation apparatus. The wafer is stopped at that point and the passageway sealed above and below the wafer by inflating a pair of resilient tubes which extend through one of the plate members and across the opening of the passageway. An airtight chamber is thus formed from which the air may be evacuated for effective ion implantation.

Abstract: A method of manufacturing a junction field effect transistor wherein after a P type pre-diffused layer is formed in an N type region constituting a back gate region of a junction field effect transistor, arsenic is selectively diffused into the P type pre-diffused layer to form a gate region with a simultaneous drive-in step for the P type pre-diffused layer in order to obtain a thin channel by utilizing the pull-in effect.

Abstract: A pulsed electron beam generator produces a short duration pulse of electrons in the form of a directed beam for thermal processing of a semiconductor device, which is positioned in a pulsed electron beam chamber so that the propagating electron beam impacts upon the device surface in selected regions of the device that are to be processed. Energy deposited by the impacting electron pulse momentarily elevates the temperature of the selected regions above threshold processing temperatures for rapid, effective annealing, sintering or other thermal processing. The characteristics of the electron beam pulse are such that only those surface vicinity regions to be processed are elevated to a high temperature, the remaining mass of the semiconductor device not being subjected to unnecessary or undesirable high temperature exposure.

Abstract: A semiconductor substrate is coated with an insulating film followed by a layer of polysilicon. The polysilicon layer is coated with a non-oxidizable mask, such as silicon nitride, and then oxidized to convert the exposed regions to silicon oxide and add further thickness to the converted oxide regions. When the mask is removed, the thicker silicon oxide regions serve as an in situ mask for selectively implanting impurity ions through the thinner polysilicon regions and into the semiconductor substrate. When the silicon oxide regions are etched away, the remaining polysilicon regions serve as an ion implantation mask for permitting selective ion implantation through the voids left by etching the silicon oxide regions.

Abstract: A method for manufacturing integrated circuits provides total self-alignment of all critically positioned device regions. Self-alignment is accomplished by a combination of selectively etchable thin layers on the surface of a semiconductor body. An initially formed predetermined pattern of openings defines all active regions of the device. Selective introduction of impurities in sub-sets of this predetermined pattern form regions of a semiconductor device in a totally self-aligned manner while ion implantation through all overlying layers provides for the formation of further shallow device regions irrespective of the predetermined pattern of openings.

Abstract: A method of making a semiconductor device for application in a monolithic integrated circuit is described wherein a local buried insulating layer is provided at the interface of a substrate and a semiconductive layer, and then the semiconductive layer is locally converted into a insulator which extends down to the buried insulator. The method is useful, among other things, for providing isolated semiconductor islands.

Abstract: A method of ion implantation into a semiconductor substrate which comprises forming a layer of an electrically insulative material, such as silicon dioxide, on the substrate over the region to be ion implanted. Then, a beam of ions having sufficient energy to pass through the layer of insulative material and to penetrate into the substrate is directed at a particular portion of the insulative layer. Before proceeding further, at least the upper half of the insulative layer, and preferably all of the upper portion of the insulative layer, in excess of a remaining thickness of 100A, is removed by etching. Then, the substrate is heated whereby the ions are driven further into the substrate to form the selected ion implanted region.

Abstract: A monocrystalline silicon wafer is prepared which has formed therein the usual emitter, base and collector regions. A groove is then formed to a predetermined depth in the top surface of the silicon wafer so as to extend along the P-N junction between the base and emitter regions. A silicon oxide layer is formed over the wafer, as by heating the same in an oxidative atmosphere, and the wafer is succeedingly heated in a hydrogenous atmosphere. The silicon oxide layer may be selectively photoetched away where the electrodes are to be formed for the emitter, base and collector of the transistor.

Abstract: Disclosed is a bidirectional triode thyristor pellet that comprises two current conductive regions and a gate region. Gold is diffused into the boundaries between the several regions to inhibit carrier migration thereacross and thus reduce turnoff time. Also disclosed is a method of fabricating the subject thyristor pellet that permits glass passivation thereof if desired.

Abstract: Disclosed is an SCR pellet and a method for the fabrication thereof. A layer of oxide is grown on a semiconductor wafer that has been diffused to form a plurality of SCR pellets and openings are etched in the oxide at locations corresponding to each pellet. Gold is diffused through the openings into a preselected distribution in the base region to reduce turnoff time. Grooves are etched to facilitate glass passivation and division of the wafer into pellets.

Abstract: An impurity concentration profile is established in a solid by attaching solid to a heat sink and irradiating it with one or more fast laser pulses. The impurity may initially be located in a surface layer or it may be dispersed throughout the solid.

Abstract: A method for improving the current confinement capacity of a double heterojunction laser by using a high energy implantation of oxygen in the regions of an injection laser surrounding the active region of such laser so as to make such regions semi-insulating.

Abstract: The disclosure relates to the formation of very thin silicon slices, 1/10 of a mil, and the mechanical strengthening of such thin silicon slices and to the formation of electronic circuitry in such slices and the use thereof. These slices are formed, in accordance with one embodiment of the invention, by etching grooves in an n+ wafer using an orientation dependent etch and etching along the {111} plane in {110} n+ wafers. After oxide removal, the surface of the wafer opposite the grooves is epitaxially coated with n-type silicon and the original grooves are then further etched by an electrolytic etch or by a concentration dependent etch which will remove only the n+ material, thereby leaving the thin wafer with a honeycomb-like supporting structure with struts in the shapes of parallelograms, diamonds and the like.

Abstract: A method for making an IGFET is described. The method utilizes impurity ion implantation into the surface channel to determine the conductivity thereof. The advantages include special impurity profiles providing improved performance, better control over important parameters such as threshold voltage, the manufacture of improved tetrodes, and the manufacture of improved ICs using for example N- and P-channel devices, and depletion and enhancement devices combined in a single chip.