Patents Examined by J. M. Davis
  • Patent number: 3935033
    Abstract: The radiation resistance of silicon transistors with a silicon oxide coating is improved by irradiating the semiconductor device with electrons at an energy below 150 keV and a dose between 10.sup.9 and 10.sup.12 rad at the boundary layer between the silicon and silicon oxide coating. The temperature of the semiconductor device is maintained at a temperature of between 150.degree. and 450.degree.C during irradiation thereof.
    Type: Grant
    Filed: November 15, 1973
    Date of Patent: January 27, 1976
    Assignee: Siemens Aktiengesellschaft
    Inventors: Rudolf Bauerlein, Dieter Uhl
  • Patent number: 3933541
    Abstract: A silicon dioxide film and a silicon nitride film are successively vapor-deposited on a main face of an N type silicon substrate processed with H.sub.2 O.sub.2 water. Those portions of both films underlaid by a P type region to be subsequently formed and their peripheral portions are selectively removed. Then a P type impurity is diffused into the central exposed portion of the main substrate face to form the P type region with a PN junction having a termination facing the silicon dioxide film. Also a silicon dioxide film is thermally formed on the peripheral exposed portion of the main face.
    Type: Grant
    Filed: January 20, 1975
    Date of Patent: January 20, 1976
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroyasu Hagino, Yasuya Kajiwara, Seiichi Nagai
  • Patent number: 3933529
    Abstract: A process for the production of a pair of complementary field effect transistors which have very short channel lengths. A lightly doped semiconductor layer is deposited on an electrically insulating substrate. A gate insulator layer is applied onto which first and second gate electrodes are formed for the two transistors. A masking oxide layer is applied to the exposed surface regions of the gate insulating layer and the gate electrodes. An opening is etched into the masking layer and gate insulator layer lying adjacent each gate electrode. Charge carriers of first and second types are diffused through the respective openings into the region of the semiconductor layer lying below to dope the same. This doping extends partially into the semiconductor region lying beneath a portion of the respective gate electrodes. All parts of the gate insulator layer except those parts lying beneath the gate electrodes are removed.
    Type: Grant
    Filed: July 10, 1974
    Date of Patent: January 20, 1976
    Assignee: Siemens Aktiengesellschaft
    Inventor: Karl Goser
  • Patent number: 3933530
    Abstract: In one embodiment, a semiconductor device, such as an insulated-gate-field-effect-transistor (IGFET), is simultaneously radiation hardened with Al ions and its threshold voltage stabilized with halide ions, such as Cl ions, by bombarding a silicon dioxide gate insulator of the device with molecular ions of an aluminum halide, such as AlCl.sub.2 .sup.+ ions. In another embodiment, a surface (target) of silicon is bombarded with molecular AlCl.sub.2 .sup.+ ions to ion implant separate Al ions and Cl ions. There, an oxide layer subsequently thermally grown on the bombarded surface includes the Al ions and the Cl ions, and the oxide layer is radiation hardened and gettered.
    Type: Grant
    Filed: January 28, 1975
    Date of Patent: January 20, 1976
    Assignee: RCA Corporation
    Inventors: Charles William Mueller, Edward Curtis Douglas, Chung Pao Wu
  • Patent number: 3933540
    Abstract: A method of manufacturing bipolar transistor elements in a semiconductor integrated circuit isolated by a silicon oxide film, comprises the steps of forming a semiconductor layer of one conductivity type on a semiconductor substrate of the opposite conductivity type, in which each collector region of the one conductivity type is formed, diffusing an impurity of the opposite conductivity type for each base region into the surface of the semiconductor layer of the one conductivity type, performing oxidation down to the surface of the semiconductor substrate by employing an oxidation-resisting film as a mask, to thereby form an isolating silicon oxide film, and diffusing an impurity of the one conductivity type for each emitter region into a selected part of the surface of the diffused semiconductor layer of the opposite conductivity type, whereby the base width of the bipolar transistor elements can be narrowed.
    Type: Grant
    Filed: August 8, 1974
    Date of Patent: January 20, 1976
    Assignee: Hitachi, Ltd.
    Inventors: Hiroyuki Kondo, Atsuo Hotta, Akio Hayasaka, Michio Suzuki
  • Patent number: 3933528
    Abstract: A self-aligning process for fabrication of integrated circuits utilizing ion implantation to effect doping. A composed masking technique is used to define self-aligned areas in a silicon oxide layer for definition of isolation, base, resistor and collector contact regions. Only two oxide removal steps are required for isolation through emitter process steps, and the process uses the silicon oxide layer and photoresist material for implantation masking. Formation of the emitter region by ion implantation and by diffusion are described.
    Type: Grant
    Filed: July 2, 1974
    Date of Patent: January 20, 1976
    Assignee: Texas Instruments Incorporated
    Inventor: Benjamin Johnston Sloan, Jr.
  • Patent number: 3933527
    Abstract: Diodes of a particular type are fine tuned with irradiation to optimize the reverse recovery time while minimizing forward voltage drop and providing more uniform electrical characteristics. The initial and desired minority carrier lifetimes in the anode region of the type are determined as a function of forward voltage drop and reverse recovery time, and the minority carrier radiation damage factor is determined for a desired type of diode and radiation source. The radiation dosage to achieve the desired carrier lifetime with the radiation source is thereafter determined from the function 1/.tau. = 1/.tau..sub.o + K.phi., where .tau. is the desired minority carrier lifetime, .tau..sub.o is the initial minority carrier lifetime, K is the determined minority carrier radiation damage factor and .phi. is the radiation dosage. A major surface and preferably the major surface adjoining the anode region of the diodes is then irradiated with the radiation source to the determined radiation dosage.
    Type: Grant
    Filed: March 9, 1973
    Date of Patent: January 20, 1976
    Assignee: Westinghouse Electric Corporation
    Inventors: Krishan S. Tarneja, John Bartko, Joseph E. Johnson
  • Patent number: 3932239
    Abstract: This disclosure is directed to a semiconductor diffusion process for diffusing impurities into a semiconductor substrate. Open tube phosphorous diffusion process conditions are described wherein diffused region depth control is achieved by the initial deposition time. This permits creation of a diffused region having the benefits of low sheet resistance and shallow depth. Additionally, the diffusion process enables the formation of very thick thermal oxide layers which are particularly useful in MOS or FET device fabrication.
    Type: Grant
    Filed: October 27, 1970
    Date of Patent: January 13, 1976
    Assignee: Cogar Corporation
    Inventor: William A. Brown
  • Patent number: 3930893
    Abstract: A method of fabricating conductivity connected charge-coupled devices (C4D's) is disclosed wherein N+ barriers are ion-implanted in an N-type substrate and wherein P++ conductivity connecting regions are formed by diffusion of impurity atoms into the substrate. The process is compatible with the known silicon gate process, enabling semiconductor devices of other types and with different thresholds to be formed on the substrate at the same time the C4D's are fabricated.
    Type: Grant
    Filed: March 3, 1975
    Date of Patent: January 6, 1976
    Assignee: Honeywell Information Systems, Inc.
    Inventor: Wallace Edward Tchon