Abstract: A dynamic memory allocator in a computer assigns portions of memory into a large number of slots that include zero or more memory blocks of equal size. Free lists identify memory blocks, corresponding to a slot size, not currently in use in the computer. Software programs generate requests, including a size, for a memory block. The size of the requests are rounded up to the nearest slot size. To allocate a memory block, the free lists are searched, using a bit map index or a hierarchical bit map index, to identify an available memory block to accommodate the memory block requested. The dynamic memory allocator handles large block allocations different from small block allocations. A virtual memory allocator stores a plurality of pointers to identify one or more virtual pages of memory for allocation to the dynamic memory allocator.

Abstract: A data prefetching arrangement for use between a computer processor and a main memory. The addresses of data to be prefetched are calculated by decoding instructions which have been prefetched by decoding prefetched instructions, the instructions having been in accordance with an intelligent prefetching scheme. The processor registers have two sections for respective access by the processor and a prefetch controller. The instruction registers may also contain an additional counter field which indicates the number of instruction cycles which must be executed before the register may be reliably utilized for prefetching data.

Abstract: A method and system are provided for recovering after a failure in a data replication environment. According to the method, a transaction is executed at a source site that makes changes that must be replicated at a destination site. The changes are made permanent at the source site. The changes are made permanent at the source site without the source site being informed as to whether the changes were successfully applied at the destination site. The changes are sent to the destination site. The changes are applied at the destination site. If the changes are successfully applied before the failure, then the changes are made permanent at the destination site and a record is added to a set of records at the destination site. The record indicates that the changes where made permanent at the destination site. After a failure, the set of records at the destination site are used to determine which changes must be sent from the source site to the destination site after the failure.

Abstract: Solid-state flash electrically erasable and programmable read-only-memory ("flash EEPROM") system is combined with a rotating disk drive memory to provide mass program and data storage in a computer system. A common memory controller directs system generated memory addresses in a disk format to either the EEPROM system or disk memory. The blocks of data handled by the EEPROM system have the same size and other attributes as sectors of data handled by the disk system, thereby making it transparent to the computer system processor as to whether it is accessing the EEPROM or disk portion of the storage system. A particular program or data file may then be stored in the portion of the memory system best suited to handle it, and thus take advantage of the different features and characteristics of EEPROM and magnetic media disk memory.

Abstract: A method and apparatus are provided for displaying image and facsimile data on a host-based application display. A host computer generates control and download command data for displaying the image or facsimile data. The image and facsimile data is processed by a non-programmable-terminal (NPT) or a programmable work station (PWS) for presentation of a display screen. When a user requests another function, the NPT or PWS stores image information and sends image information to the host computer. The save image information includes cache image counter data, scaling and viewed image screen location data that is used to restore the displayed image and facsimile data when the user returns to the previous function.

Abstract: In accordance with the present invention, a programmable array includes hierarchical configuration and state storage. The array comprises an active storage for an active configuration and an active state as well as an inactive storage for one or more inactive configurations and one or more inactive states. The array further comprises logic and routing configured by the active configuration. The logic includes a plurality of combinational elements and a plurality of sequential logic elements for providing the states. Bits are transferred between the active and the inactive storage.

Abstract: In each of the information processing apparatuses connected to each other via a network, there is arranged a quality of service (QOS) table to which functions and performance thereof are registered. When an information processing apparatus is additionally linked with the network, a QOS table thereof is automatically registered to a local directory of the network such that an agent converts the contents of the QOS table into service information to be supplied via a user interface to the user. Thanks to the operation, information of functions and performance of each information processing apparatus connected to the network is converted into service information for the user. Consequently, the user can much more directly receive necessary services.

Abstract: An electronic component including an electrically erasable non-volatile memory for storing information structured in logical entities that are managed by a memory manager. The memory is segmented into pages for the purpose of erasing the information. The memory manager is programmed to organize at least one type of logical entity into pages. Each of the logical entities occupies, at least in part, an integer number of pages in an exclusive manner. This technique is applicable to electronic components to which the electrical power supply is liable to be interrupted in an untimely manner.

Abstract: A data processor (10) has a load/store unit (28) that executes store-to-shared-data instructions before it exclusively owns the data designated by the instruction. Later, a bus interface unit (12) performs a snoop transaction to obtain exclusive ownership of the data. If data processor successfully obtains such ownership, then the data processor correctly and quickly executed the instruction with no further action required. If the data processor can not obtain ownership of the data, then data processor re-executes the instruction in the same time as if it had not acted speculatively.

Abstract: A method and apparatus for enabling the detection of memory presence and identification of memory type in a memory system. A memory controller may be connected to a memory bank which may be inserted into a memory bank insertion area, via an interconnect line which, in a preferred embodiment, may be a select line commonly used to activate or deactivate the memory banks. Presence detect signals are multiplexed over the interconnect line for detecting whether a memory bank is connected to a given line. For connected memory banks a type detection signal is multiplexed over the interconnect line for detecting the type of memory bank connected thereto. The presence and type detection operations generate output signals to permit the dynamic configuration of a memory system controller.

Abstract: An asynchronous access system for a computer system includes processing modules performing processes, at least one shared system memory module, and a system bus connecting the processing modules and the shared system memory module. Each of the processing modules includes a processor, a plurality of buffers coupled to the processor and to the system bus, and a controlling unit for writing data from the plurality of processors into the shared system memory module. Data is written into the shared system memory module by a processor generating write instructions to write data via the plurality of buffers and the system bus. The controlling unit controls the writing such that one writing instruction writes data into a plurality of buffers, then transfers the data to the shared system memory module via the system bus, with another writing instruction writing additional data into another plurality of buffers and transferring the additional data to the shared system memory module.

Abstract: An information recording/reproducing apparatus wherein the CPU stores data transferred through an interface in a temporary storage area and later records the data in a recording medium by using a recording/reproducing means. The temporary storage area is divided into first and a second regions by a temporary storage region disposition device. A discriminator determines whether the process-requested region is an information managing region or a data region from the process requests made by the host computer and the temporary storage region managing information. Based on the result of this discrimination, the temporary storage region manager allocates the first region if the data is for information managing or the second region if the data is intended for data storage.

Abstract: A dynamic storage device requires periodic refresh and includes logical operation circuitry within the refresh circuitry. The individual storage positions of the storage device are periodically read by a refresh amplifier, and then a logical operation is performed on the refresh data before the data re applied to the write amplifier. That operation allows implementation of associative database searching by cyclically executing "data compare" and other logical operations within the refresh circuitry. A system of content searching may be implemented in any storage device, dynamic or not, in which a comparand may be matched with any of a plurality of subunits of a word, and a storage bit is used to identify any words in which a mismatch occurs.

Abstract: A method and system for providing access to a protected partition of a direct access storage device in a data processing system which includes a direct access storage device, an adapter that commands I/O of the storage device and also contains a protection mechanism that restricts access to a memory partition on the storage device, an adapter device driver for controlling the adapter, and a system block device driver for transferring I/O commands to the system partition from the operating system to the adapter device driver. The method comprises the steps of receiving a request to perform a read or write to a protected memory partition, generating a command data block directing the storage device to perform the read or write, and generating a passthru command containing the command data block that directs the adapter to send the command data block without enforcing the protection of the memory partition.

Abstract: A dynamic random access memory (RAM) addressing controller comprises a plurality of connectors connectible with a plurality of memory boards which use different addressing arrangements. A timing generator for generating a timing signal is provided for multiplexing address signals applied to a dynamic RAM storage. The controller also includes an input unit for applying an address signal of predetermined width, an address selector for mutliplexing a part of the address signal supplied from the input unit in accordance with the timing signal, a branching unit for supplying another part of the address signal of predetermined width from the input unit to a corresponding portion of each of the connectors respectively, and another branching unit for branching the address signal of the multiplexed part from the address selector in such a way as to be applied to a corresponding portion of each of the connectors. Memory boards carrying highly-integrated memory devices are replaceable in memory board slots.

Abstract: A cache controller for a cache memory having a number of cache lines includes a page index monitor and a page index tracker coupled to the page index monitor. The page index monitor is configured to update a thrashing value associated with a cache line identified by a first page index. The page index includes a tracking controller and a replacement tracking store. The tracking controller is configured to store a first tag and a second tag in the replacement tracking store when a first data stored in the cache line is replaced with a second data where the first data is also stored in a first main memory location identified by a first address having said first page index and said first tag, and the second data is stored in a second main memory location identified by a second address having the first page index and the second tag.

Abstract: An apparatus and method for reducing the time required to supply a processor core with instructions uses a cache memory, a cache controller, and an instruction predecoding unit. When a line of instructions is retrieved into the cache memory, the instruction predecoding unit inspects the instructions in the line to determine if the line contains any nonsequential instructions. The cache controller stores an indication of whether the line contains nonsequential instructions with the line of instructions in the cache memory. If a given line of instructions does not contain any nonsequential instructions, the line of instructions following the given line is retrieved into the cache memory when one of the instructions in the given line is requested by the processor core.

Abstract: A fault tolerant computer which executes the cache flush operation at a high speed and has the real time characteristic. A processor module 301 is equipped with a cache memory so that the entry address of the updated cache block within the cache memory is stored in a stack. The cache flush is effected only with respect to the entry address in the stack when a recovery-point setting condition due to a timer or the like is satisfied. A memory module 303 has an arrangement doubled in the same storage physical space and is equipped with a buffer memory for temporarily storing the transferred cache block, so that the cache block is simultaneously transferred to a pair of buffer memories.

Abstract: A bus interface is connected to a system bus for monitoring a bus command indicating that data is updated on a cache memory of a processor. If the data is updated on the cache memory, the external tag storage device stores state information to indicate the update of the data and a physical address corresponding to the updated data. An external tag reading device reads the state information stored in the external tag storage device, when the updated data on the cache memory is stored in a main memory. A bus command for flushing the updated data from the cache memory to the main memory is generated, based on the state of the tag read out from the external tag storage device. An invalid bus command generation device outputs an invalid bus command to the system bus through a FIFO.

Abstract: In an .chi.86-compatible processor capable of operating in a protected mode of operation in which privilege levels are assigned to tasks executing therein, an application task being assigned a lowest privilege level and executable in the processor to cause the processor to calculate addresses corresponding to specific locations in a computer memory associated with the processor, the addresses to be in alignment with respect to the computer memory prior to the processor issuing the addresses, a circuit for, and method of, handling sequential alignment faults and a computer system embodying the same.