Patents Examined by Jae Lee
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Patent number: 11476348Abstract: A manufacturing method of a semiconductor device includes the following steps. First patterned structures are formed on a substrate. Each of the first patterned structures includes a first semiconductor pattern and a first bottom protection pattern disposed between the first semiconductor pattern and the substrate. A first protection layer is formed on the first patterned structures and the substrate. A part of the first protection layer is located between the first patterned structures. A first opening is formed in the first protection layer between the first patterned structures. The first opening penetrates the first protection layer and exposes a part of the substrate. A first etching process is performed after forming the first opening. A part of the substrate under the first patterned structures is removed by the first etching process for suspending at least a part of each of the first patterned structures above the substrate.Type: GrantFiled: January 19, 2021Date of Patent: October 18, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chuan-Chang Wu, Zhen Wu, Hsuan-Hsu Chen, Chun-Lung Chen
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Patent number: 11469367Abstract: A method for separating a removable composite structure using a light flux includes supplying the removable composite structure, which successively comprises: a substrate that is transparent to the light flux; an optically absorbent layer for at least partially absorbing a light flux; a sacrificial layer adapted to dissociate subject to the application of a temperature higher than a dissociation temperature and made of a material different from that of the optically absorbent layer; and at least one layer to be separated. The method further includes applying a light flux through the substrate, the light flux being at least partly absorbed by the optically absorbent layer, so as to heat the optically absorbent layer; heating the sacrificial layer by thermal conduction from the optically absorbent layer, up to a temperature that is greater than or equal to the dissociation temperature; and dissociating the sacrificial layer under the effect of the heating.Type: GrantFiled: March 22, 2019Date of Patent: October 11, 2022Assignee: SoitecInventors: Jean-Marc Bethoux, Guillaume Besnard, Yann Sinquin
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Patent number: 11462424Abstract: The present invention is related to a heating device for heating an object material using a laser beam, the heating device comprising a stage on which the object material is placed; a laser module for generating and outputting a laser beam; an optical module for controlling a path of the laser beam; a polygon mirror rotating around an axis of rotation and having a plurality of reflecting surfaces which reflect the laser beam; and a beam guide module for controlling an incidence range within which the laser beam reflected by the polygon mirror is incident on the object material, and an indirect heating method using a laser beam in a heating device.Type: GrantFiled: January 30, 2018Date of Patent: October 4, 2022Assignee: RNR LAB INC.Inventor: Jeong Do Ryu
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Patent number: 11450578Abstract: A substrate processing system includes: a modification layer forming device configured to form a modification layer within a first substrate along a boundary between a peripheral portion to be removed and a central portion of the first substrate; an interface processing device configured to process an interface where the first substrate and a second substrate are bonded in the peripheral portion; a periphery removing device configured to remove the peripheral portion starting from the modification layer; a position detection device configured to detect a position of the modification layer or a position of the interface; and a control device configured to control the modification layer forming device and the interface processing device. The control device controls the position of the interface based on the detected position of the modification layer, or controls the position of the modification layer based on the detected position of the interface.Type: GrantFiled: April 15, 2019Date of Patent: September 20, 2022Assignee: TOKYO ELECTRON LIMITEDInventor: Hayato Tanoue
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Patent number: 11450838Abstract: Provided are a display panel, a manufacturing method thereof and a display device. The display panel includes a substrate, multiple light-emitting elements and a circular polarizer. The multiple light-emitting elements are disposed on one side of the substrate. The circular polarizer is disposed on one side of the multiple light-emitting elements facing away from the substrate. The circular polarizer is provided with first hollow structures corresponding to at least part of the multiple light-emitting elements. The area where each first hollow structure is located overlaps a respective one of the at least part of the multiple light-emitting elements.Type: GrantFiled: December 15, 2020Date of Patent: September 20, 2022Assignee: Hubei Yangtze industrial Innovation Center Of Advanced Display Co., Ltd.Inventors: Linshan Guo, Shaorong Yu
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Patent number: 11444129Abstract: A display panel a display device are provided. The display panel includes a plurality of pixel units arranged in a row direction and in a column direction, the display panel includes a display region. An edge of the display region includes a fold line formed by connecting a line segment extending in the row direction and a line segment extending in the column direction, a parallelogram region formed in the display region taking two adjacent line segments as adjacent sides includes the pixel units; directions from an intersection point of the two adjacent line segments to end points of the two adjacent line segments other than those at the intersection point are a first direction and a second direction, respectively; in the parallelogram region, aperture ratios of the pixel units arranged in at least one of the first direction and the second direction increase gradually.Type: GrantFiled: May 25, 2018Date of Patent: September 13, 2022Assignees: CHENGDU BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.Inventors: Yin Deng, Bo Wu, Xiaojing Qi
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Patent number: 11444217Abstract: A method for producing a thin-film solar module with serially connected solar cells and related device. A back electrode layer is deposited on one side of a flat substrate and subdivided by first patterning trenches. An absorber layer is deposited over the back electrode layer and subdivided by second patterning trenches. A front electrode layer is deposited over the absorber layer. At least the front electrode layer is subdivided by third patterning trenches. A direct succession of a first patterning trench, a second patterning trench, and two adjacent third patterning trenches forms a patterning zone. The third patterning trenches are produced by laser ablation through a pulsed laser beam, where one third patterning trench is produced with laser pulses of higher energy and the other third patterning trench of the patterning zone is produced with laser pulses of lower energy.Type: GrantFiled: February 8, 2019Date of Patent: September 13, 2022Assignee: CNBM RESEARCH INSTITUTE FOR ADVANCED GLASS MATERIALS GROUP CO., LTD.Inventors: Andreas Heiss, Helmut Vogt
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Patent number: 11443966Abstract: Systems, apparatuses, and methods are provided for predicting or determining irregular processing parameters during processing of a semiconductor wafer in a semiconductor processing apparatus, such as an etching apparatus. A semiconductor processing apparatus includes a load port that is configured to receive a semiconductor wafer. A process chamber is coupled to the load port, and a fan is configured to selectively vary a flow of fluid in the process chamber. One or more sensors are provided in the process chamber and are configured to sense one or more processing parameters in the process chamber. A controller is coupled to the one or more sensors and to the fan, and the controller is configured to control the fan to vary the flow of fluid in the process chamber based on the sensed one or more processing parameters.Type: GrantFiled: January 17, 2020Date of Patent: September 13, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Kai-Chin Wei, Che-fu Chen
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Patent number: 11444256Abstract: This invention provides a filter-free tunable spectrum PD with a layered structure of at least two electrodes and two functional layers. Both functional layers can be a layer, a stack of inorganic semiconductors, an organic semiconductor, an organic/polymer donor/acceptor blend, a hybrid semiconductor or their combinations that has a good charge transport property. The first functional layer absorbs the shorter-wavelength EM waves and is transparent to the longer-wavelength EM waves. The second functional layer absorbs the longer-wavelength EM waves. The detection spectrum window is determined by the difference in wavelengths between the transmission cut-off wavelength of the first functional layer and absorbing edge of the second functional layer, or between the absorption edge of the first functional layer and that of the second functional layer.Type: GrantFiled: June 22, 2020Date of Patent: September 13, 2022Assignee: Hong Kong Baptist UniversityInventors: Furong Zhu, Zhaojue Lan
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Patent number: 11437559Abstract: A physical vapor deposition system includes a chamber, three target supports to targets, a movable shield positioned having an opening therethrough, a workpiece support to hold a workpiece in the chamber, a gas supply to deliver nitrogen gas and an inert gas to the chamber, a power source, and a controller. The controller is configured to move the shield to position the opening adjacent each target in turn, and at each target cause the power source to apply power sufficient to ignite a plasma in the chamber to cause deposition of a buffer layer, a device layer of a first material that is a metal nitride suitable for use as a superconductor at temperatures above 8° K on the buffer layer, and a capping layer, respectively.Type: GrantFiled: March 18, 2020Date of Patent: September 6, 2022Assignee: Applied Materials, Inc.Inventors: Mingwei Zhu, Zihao Yang, Nag B. Patibandla, Ludovic Godet, Yong Cao, Daniel Lee Diehl, Zhebo Chen
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Patent number: 11437258Abstract: A method for storage a workpiece used in fabrication of a semiconductor device includes disposing the workpiece on a workpiece carrier, disposing the workpiece carrier with the workpiece in a workpiece container via a workpiece storage system, identifying a content of the workpiece container, and adjusting a storage condition inside the workpiece container in response to the content of the workpiece container via the workpiece storage system.Type: GrantFiled: July 24, 2019Date of Patent: September 6, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tzu-Chi Chiu, Jen-Ti Wang, Ting-Wei Wang, Kuo-Fong Chuang
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Patent number: 11417548Abstract: A component mounting machine includes a control device that controls a wafer supply device and a component transfer device. The control device includes a die information storage section storing the position of the dies stored in the wafer supply device associated with a rank of the dies, a block information acquisition section acquiring the condition of the dies to be mounted on a block provided on a board, a rank designation section designating the rank of the die to be picked up by the component transfer device, and a position designation section designating the position of the die to be picked up by the component transfer device. The position designation section designates the position of the die so that the die having the rank designated by the rank designation section is continuously picked up over the multiple wafers stored in the wafer supply device.Type: GrantFiled: March 9, 2017Date of Patent: August 16, 2022Assignee: FUJI CORPORATIONInventors: Yukinori Nakayama, Shinichi Fujii
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Patent number: 11417646Abstract: An integrated circuit formed on a silicon substrate includes an NMOS transistor with n-channel raised source and drain (NRSD) layers adjacent to a gate of the NMOS transistor, a PMOS transistor with SiGe stressors in the substrate adjacent to a gate of the PMOS transistor, and an NPN heterojunction bipolar transistor (NHBT) with a p-type SiGe base formed in the substrate and an n-type silicon emitter formed on the SiGe base. The SiGe stressors and the SiGe base are formed by silicon-germanium epitaxy. The NRSD layers and the silicon emitter are formed by silicon epitaxy.Type: GrantFiled: June 3, 2016Date of Patent: August 16, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Manoj Mehrotra, Terry J. Bordelon, Deborah J. Riley
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Patent number: 11411103Abstract: The current disclosure describes a tunnel FET device including a P-I-N heterojunction structure. A high-K dielectric layer and a metal gate wrap around the intrinsic channel layer with an interlayer positioned between high-K dielectric layer and the intrinsic channel layer of the P-I-N heterojunction. The interlayer prevents charge carriers from reaching the interface with high-K dielectric layer under the trap-assisted tunneling effect and reduces OFF state leakage.Type: GrantFiled: May 12, 2020Date of Patent: August 9, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Timothy Vasen, Gerben Doornbos, Matthias Passlack
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Patent number: 11411139Abstract: Textured optoelectronic devices and associated methods of manufacture are disclosed herein, in several embodiments, a method of manufacturing a solid state optoelectronic device can include forming a conductive transparent texturing material on a substrate. The method can further include forming a transparent conductive material on the texturing material. Upon heating the device, the texturing material causes the conductive material to grow a plurality of protuberances. The protuberances can improve current spreading and light extraction from the device.Type: GrantFiled: July 7, 2020Date of Patent: August 9, 2022Assignee: Micron Technology, Inc.Inventors: Lifang Xu, Scott D. Schellhammer, Shan Ming Mou, Michael J. Bernhardt
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Patent number: 11404384Abstract: An interconnect structure includes a first and second insulating layer, a first and second conductive line, and a first, second, and third conductive via. The second insulating layer is disposed on the first insulating layer. The first conductive line including a first and second portion, and the first, second, and the third conductive vias are embedded in the first insulating layer. The second conductive line including a third portion and fourth portion is embedded in the second insulating layer. The first conductive via connects the first and third portions. The second conductive via connects the second and third portions. The third conductive via connects the second and fourth portions. A first cross-sectional area surrounded by the first, second, third portions, the first, second conductive vias is substantially equal to a second cross-sectional area surrounded by the second, third, fourth portions, the second, third conductive vias.Type: GrantFiled: November 25, 2020Date of Patent: August 2, 2022Assignee: NANYA TECHNOLOGY CORPORATIONInventors: Ting-Cih Kang, Hsih-Yang Chiu
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Patent number: 11404679Abstract: A method of preparing a film and a light-emitting device are disclosed. The method includes: providing at least one gas-phase source above a substrate, the at least one gas-phase source made of materials comprising a perovskite material; and controlling an evaporation rate of the at least one gas-phase source to form a perovskite film. In the method provided by the present invention, a perovskite light-emitting layer is prepared by gas-phase source evaporation coating without an organic solvent, which avoids miscibility between the organic solvent and other layers and improves compatibility between the perovskite material and other film materials, thereby realizing the low preparation cost and the simple preparation process.Type: GrantFiled: November 26, 2019Date of Patent: August 2, 2022Inventors: Pei Jiang, Chiayu Lee, Chunche Hsu, Shujhih Chen, Miao Duan, Yongming Yin, Yongwei Wu, Bo He
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Patent number: 11404658Abstract: The present disclosure is related to a method of manufacturing a light-emitting layer. The method of manufacturing a light-emitting layer may include forming a layer of metal first halide perovskite on a substrate, forming a first pattern comprising metal second halide perovskite in the layer of metal first halide perovskite, and forming a second pattern comprising metal third halide perovskite in the layer of metal first halide perovskite.Type: GrantFiled: January 16, 2019Date of Patent: August 2, 2022Assignee: BOE TECHNOLOGY GROUP CO., LTD.Inventor: Boris Kristal
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Patent number: 11387403Abstract: A piezoelectric bimorph cantilever beam system includes a shim having a first main surface, a second main surface opposite the first main surface, a proximal end connected to an anchor, and a distal end opposite the proximal end. The system further includes a first piezoelectric layer laminated on the first main surface of the shim and a second piezoelectric layer laminated on the second main surface of the shim. A first beam stiffener is provided over the first main surface of the shim adjacent to the anchor with the first beam stiffener at least partially covering the first piezoelectric layer. A second beam stiffener is provided over the second main surface of the shim adjacent to the anchor with the second beam stiffener at least partially covering the second piezoelectric layer.Type: GrantFiled: July 5, 2018Date of Patent: July 12, 2022Assignees: VERMON S.A., UNIVERSITE GRENOBLE ALPESInventors: Libor Rufer, Skandar Basrour, Emilie Trioux, Guillaume Férin, Claire Bantignies, Hung Le Khanh, Bogdan Rosinski, An Nguyen-Dinh
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Patent number: 11387374Abstract: A method for assembling an optoelectronic package assembly includes engaging a connector holder with a substrate, the connector holder defining an engagement feature and the substrate including optical waveguides, engaging a connector of a fiber array unit with the engagement feature the connector holder where the engagement feature retains the connector and where the fiber array unit includes the connector and optical fibers coupled to the connector, optically coupling the optical fibers to the optical waveguides of the substrate, heating the connector holder, the fiber array unit, the substrate, and a solder positioned between the substrate and a base substrate, where the heating is sufficient to melt the solder, and cooling the solder to couple the substrate to the base substrate.Type: GrantFiled: November 2, 2020Date of Patent: July 12, 2022Assignee: Corning Research & Development CorporationInventors: Douglas Llewellyn Butler, James Scott Sutherland