Abstract: An imaging element including: a photoelectric conversion layer including a compound semiconductor material; a contact layer disposed to be stacked on the photoelectric conversion layer and including a diffusion region of first electrically-conductive type impurities in a selective region; a first insulating layer provided to be opposed to the photoelectric conversion layer with the contact layer interposed therebetween and having a first opening at a position facing the diffusion region; and a second insulating layer provided to be opposed to the contact layer with the first insulating layer interposed therebetween and having a second opening that communicates with the first opening and is smaller than the first opening.

Abstract: The present disclosure provides a display panel and a display device. The display panel includes a plurality of auxiliary pixel driving circuits. Each of the auxiliary pixel driving circuits includes transistors, and each of the transistors includes an active layer and an insulation layer. The display panel is defined with first dummy holes in a transition display area, and the first dummy holes penetrate a part of the insulation layer away from the active layer in order to reduce difference in electrical properties between the auxiliary pixel driving circuits through the first dummy holes, thereby achieving display uniformity of the display panel.

Abstract: A semiconductor structure includes a substrate, a conductive via and a first insulation layer. The conductive via is through the substrate. The first insulation layer is between the substrate and the conductive via. A first surface of the first insulation layer facing the substrate and a second surface of the first insulation layer facing the conductive via are extended along different directions.

Abstract: The present invention relates to an electrical component for a microelectromechanical systems (MEMS) device, in particular, but not limited to, an electromechanical actuator.

Abstract: Provided is a method of manufacturing a silicon carbide epitaxial wafer appropriate for suppressing an occurrence of a triangular defect. A method of manufacturing a silicon carbide epitaxial wafer includes: an etching process of etching a surface of a silicon carbide substrate at a first temperature using etching gas including H2; a process of flattening processing of flattening the surface etched in the etching process, at a second temperature using gas including H2 gas, first Si supply gas, and first C supply gas; and an epitaxial layer growth process of performing an epitaxial growth on the surface flattened in the process of flattening processing, at a third temperature using gas including second Si supply gas and second C supply gas, wherein the first temperature T1, the second temperature T2, and the third temperature T3 satisfy T1>T2>T3.

Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first bonding surface. The bonded structure can further include a second element that has a second bonding surface. The first and second bonding surfaces are bonded to one another along a bonding interface. The bonded structure can also include an integrated device that is coupled to or formed with the first element or the second element. The bonded structure can further include a channel that is disposed along the bonding interface around the integrated device to define an effectively closed profile The bonded structure can also include a getter material that is disposed in the channel. The getter material is configured to reduce the diffusion of gas into an interior region of the bonded structure.

Abstract: An integrated circuit interconnect level including a lower metallization line vertically spaced from upper metallization lines. Lower metallization lines may be self-aligned to upper metallization lines enabling increased metallization line width without sacrificing line density for a given interconnect level. Combinations of upper and lower metallization lines within an interconnect metallization level may be designed to control intra-layer resistance/capacitance of integrated circuit interconnect. Dielectric material between two adjacent co-planar metallization lines may be recessed or deposited selectively to the metallization lines. Supplemental metallization may then be deposited and planarized. A top surface of the supplemental metallization may either be recessed to form lower metallization lines between upper metallization lines, or planarized with dielectric material to form upper metallization lines between lower metallization lines.

Abstract: An apparatus and method is provided for coating a surface of a material with a film of porous coordination polymer. A first substrate having a first surface to be coated is positioned in a processing chamber such that the first surface is placed in a substantially opposing relationship to a second surface. In some embodiments, the second surface is provided by a wall of the processing chamber, and in other embodiments the second surface is provided by a second substrate to be coated. The first substrate is held such that a gap exists between the first and second surfaces, and the gap is filled with at least one reaction mixture comprising reagents sufficient to form the crystalline film on at least the first surface. A thin gap (e.g., having a thickness less than 2 mm) between the first and second surfaces is effective for producing a high quality film having a thickness less than 100 ?m.

Abstract: A method for manufacturing a wavelength conversion member, includes: providing a wavelength conversion layer having a phosphor-containing portion and a light reflecting portion surrounding the phosphor-containing portion, and the wavelength conversion layer having an upper surface, a bottom surface and at least one side surface; forming a light-blocking film on the upper surface of the wavelength conversion layer; and removing a part of the light-blocking film by laser processing to expose at least a part of the phosphor-containing portion from the light-blocking film.

Abstract: In some embodiments, the present disclosure relates to a method of forming an interconnect. The method includes forming an etch stop layer (ESL) over a lower conductive structure and forming one or more dielectric layers over the ESL. A first patterning process is performed on the one or more dielectric layers to form interconnect opening and a second patterning process is performed on the one or more dielectric layers to increase a depth of the interconnect opening and expose an upper surface of the ESL. A protective layer is selectively formed on sidewalls of the one or more dielectric layers forming the interconnect opening. A third patterning process is performed to remove portions of the ESL that are uncovered by the one or more dielectric layers and the protective layer and to expose the lower conductive structure. A conductive material is formed within the interconnect opening.

Abstract: Provided is a semiconductor film having a corundum-type crystal structure composed of ?-Ga2O3 or an ?-Ga2O3 solid solution and the crystal defect density on at least one surface of the semiconductor film is 1.0×106/cm2 or less.

Abstract: A semiconductor device includes a semiconductor substrate; a plurality of channel regions, including a p-type channel region and an n-type channel region, disposed over the semiconductor substrate; and a gate structure. The gate structure includes a gate dielectric layer disposed over the plurality of channel regions and a work function metal (WFM) structure disposed over the gate dielectric layer. The WFM structure includes an n-type WFM layer over the n-type channel region and not over the p-type channel region and further includes a p-type WFM layer over both the n-type WFM layer and the p-type channel region. The gate structure further includes a fill metal layer disposed over the WFM structure and in direct contact with the p-type WFM layer.

Abstract: A film thickness measurement apparatus includes: a stage that places a substrate having a film formed thereon and measures a thickness of the film in-situ in a film forming apparatus; a film thickness meter including a light emitter that emits light toward the substrate disposed on the stage and a light receiving sensor that receives the light reflected by the substrate for measuring the thickness of the film in-situ; a moving mechanism including a multi-joint arm that moves an irradiation point of the light on the substrate; a distance meter that measures a distance between the light receiving sensor and the irradiation point on the substrate; and a distance adjustor that adjusts the distance between the light receiving sensor and the irradiation point on the substrate.

Abstract: Provided is a semiconductor material having improved oxidation resistance. The semiconductor material has a single crystal represented by the following composition formula: Mg2Sn·Zna??Composition formula: in which, a is a Zn content of from 0.05 to 1 at % relative to Mg2Sn.

Abstract: A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a source electrode, a drain electrode, a gate electrode and a single field plate. The source electrode, the drain electrode, and the gate electrode are disposed on the second nitride-based semiconductor layer. The gate electrode is between the source and drain electrodes. The single field plate is disposed over the gate electrode and extends toward the drain electrode. The field plate has a first end part, a second end part and the central part. The first and the second end parts are located at substantially the same height. Portions of the central part are in a position lower than that of the first and second end parts, and the first end part extends laterally in a length greater than a width of the gate electrode.

Abstract: A method for manufacturing a semiconductor structure includes preparing a dielectric structure formed with trenches respectively defined by lateral surfaces of the dielectric structure, forming spacer layers on the lateral surfaces, filling an electrically conductive material into the trenches to form electrically conductive features, selectively depositing a blocking layer on the dielectric structure, selectively depositing a dielectric material on the electrically conductive features to form a capping layer, removing the blocking layer and the dielectric structure to form recesses, forming sacrificial features in the recesses, forming a sustaining layer to cover the sacrificial features; and removing the sacrificial features to obtain the semiconductor structure formed with air gaps confined by the sustaining layer and the spacer layers.

Abstract: A method for manufacturing a semiconductor structure includes forming a plurality of dummy structures spaced apart from each other, forming a plurality of dielectric spacers laterally covering the dummy structures to form a plurality of trenches defined by the dielectric spacers, filling a conductive material into the trenches to form electrically conductive features, selectively depositing a capping material on the electrically conductive features to form a capping layer, removing the dummy structures to form a plurality of recesses defined by the dielectric spacers, filling a sacrificial material into the recesses so as to form sacrificial features, depositing a sustaining layer on the sacrificial features, and removing the sacrificial features to form air gaps confined by the sustaining layer and the dielectric spacers.

Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes a first interconnect dielectric layer arranged over a substrate. An interconnect wire extends through the first interconnect dielectric layer, and a barrier structure is arranged directly over the interconnect wire. The integrated chip further includes an etch stop layer arranged over the barrier structure and surrounds outer sidewalls of the barrier structure. A second interconnect dielectric layer is arranged over the etch stop layer, and an interconnect via extends through the second interconnect dielectric layer, the etch stop layer, and the barrier structure to contact the interconnect wire.

Abstract: The present application discloses a method for fabricating a semiconductor device. The method includes providing a substrate, forming a first conductive layer above the substrate, concurrently forming a bottom conductive layer and a redistribution structure above the first conductive layer, forming a programmable insulating layer on the bottom conductive layer, and forming a top conductive layer on the programmable insulating layer. The bottom conductive layer, the programmable insulating layer, and the top conductive layer together configure a programmable unit. The bottom conductive layer and the redistribution structure are electrically coupled to the first conductive layer.

Abstract: A method of forming an interconnect structure for semiconductor devices is described. The method comprises depositing an etch stop layer on a substrate by physical vapor deposition followed by in situ deposition of a metal layer on the etch stop layer. The in situ deposition comprises flowing a plasma processing gas into the chamber and exciting the plasma processing gas into a plasma to deposit the metal layer on the etch stop layer on the substrate. The substrate is continuously under vacuum and is not exposed to ambient air during the deposition processes.