Abstract: Systems and methods that address an optimized method to have a visual representation of qubit stochastic errors. A visual representation is generated of qubit stochastic errors that provides a platform to analyze impact on performance of a quantum circuit to facilitate understanding how noise and error impacts circuit results. Stochastic errors accumulated throughout a circuit are visualized using a gradient overlay.

Abstract: Presented embodiments facilitate efficient and effective diagnostic of test system operations, including temperature control of test equipment components. In one embodiment a test equipment diagnostic method includes applying a known/expected first bit pattern to a test equipment component, applying a known/expected second bit pattern to a test equipment component, and performing a test equipment temperature control analysis based upon the results of applying the known/expected first bit pattern and known/expected second bit pattern. The first bit pattern and second bit pattern have known/expected respective thermal loads and corresponding respective first known/expected/expected temperature and second known/expected/expected temperature. In one embodiment, performing a test equipment temperature control analysis includes determining if temperature control components control a temperature of the test equipment component within acceptable tolerances.

Abstract: Systems and methods for performing open-loop quantum error mitigation using quantum measurement emulations are provided. The open-loop quantum error mitigation methods do not require the performance of state readouts or state tomography, reducing hardware requirements and increasing overall computation speed. To perform a quantum measurement emulation, an error mitigation apparatus is configured to stochastically apply a quantum gate to a qubit or set of qubits during a quantum computational process. The stochastic application of the quantum gate projects the quantum state of the affected qubits onto an axis, reducing a trace distance between the quantum state and a desired quantum state.

Abstract: Techniques are described for wireless communication. One method includes segmenting a payload into a plurality of code blocks; generating, for each code block, a cyclic redundancy check (CRC); encoding each code block and associated CRC in one or more codewords of a plurality of codewords; and transmitting the codewords. The encoding is based at least in part on a low density parity check code (LDPCC) encoding type. Another method includes receiving a plurality of codewords associated with a payload encoded using a LDPCC encoding type; decoding a set of the codewords associated with the first payload and a CRC; and transmitting one of an acknowledgement (ACK) or a non-acknowledgement (NAK) for the set of the codewords.

Abstract: Described herein are embodiments related to defect detection in memory components of memory systems with time-varying bit error rate. A processing device determines that a bit error rate (BER) corresponding to a read operation to read a unit of data in a memory component satisfies a threshold criterion, determines a write-to-read (W2R) delay for the read operation, wherein the W2R delay comprises a difference between a time of the read operation and a write timestamp indicating when the unit of data was written to the memory component, and determines whether the W2R delay is within a W2R delay range corresponding to an initial read voltage level used by the read operation to read the unit of data. The processing device initiates a defect detection operation responsive to the W2R delay being within the W2R delay range, the defect detection operation to detect time-varying defects in the memory component.

Abstract: A temperature measurement circuit includes a band-gap reference circuit configured to generate a band-gap reference voltage that is fixed regardless of an operation temperature, a reference voltage generator circuit configured to generate a measurement reference voltage by adjusting the band-gap reference voltage, a sensing circuit configured to generate a temperature-variant voltage based on a bias current, where the temperature-variant voltage is varied depending on the operation temperature, an analog-digital converter circuit configured to generate a first digital code indicating the operation temperature based on the measurement reference voltage and the temperature-variant voltage, and an analog built-in self-test (BIST) circuit configured to generate a plurality of flag signals indicating whether each of the band-gap reference voltage, the measurement reference voltage, and a bias voltage corresponding to the bias current is included in a predetermined range.

Abstract: An interconnect offload component arranged to operate in an offloading mode, and a memory access component for enabling access to a memory element for functional data transmitted over a debug network of a signal processing device. In the offloading mode the interconnect offload component is arranged to receive functional data from an interconnect client component for communication to a destination component, and forward at least a part of the received functional data to a debug network for communication to the destination component via the debug network. The memory access component is arranged to receive a debug format message transmitted over the debug network, extract functional data from the received debug format message, said functional data originating from an interconnect client component for communication to a memory element, and perform a direct memory access to the memory element comprising the extracted functional data.

Abstract: The purpose of the present invention is to avoid ACK/NACK collision in a system in which E-PDCCH control information is transmitted, increase the utilization efficiency of ACK/NACK resources, and suppress unnecessary PUSCH band reduction. A wireless communications terminal having a configuration comprising: a reception unit that receives control signals including ACK/NACK indexes, via an expanded physical downlink control channel; a control unit that determines, on the basis of the ACK/NACK indexes, whether to use a dynamically allocated dynamic ACK/NACK resource or a specified resource specified beforehand, to send downlink data ACK/NACK signals; and a transmission unit that sends the ACK/NACK signals using the dynamic ACK/NACK resource or the specified resource, as determined.

Abstract: Performing quantum file pattern searching is disclosed herein. In one example, a quantum search service executing on a quantum computing device receives, from a requestor, a search request including a search pattern. Upon receiving the search request, the quantum search service accesses a quantum file registry of a quantum file that includes a plurality of qubits. Based on the quantum file registry record, the quantum search service identifies the plurality of qubits, as well as the locations of each qubit of the plurality of qubits. The quantum search service then accesses a plurality of data values stored by the plurality of qubits, and compares the data values to the search pattern. If the quantum search service determines that one or more data values of the plurality of data values correspond to the search pattern, the quantum search service sends to the requestor a search response indicating a match.

Abstract: Systems and methods are provided for coordinating decisions between noncommunicating parties using quantum physics. The procedure includes recognizing and identifying features of a coordinating decisions between non-communicating parties (CDNP) problem, expressing these features in a precise and mathematical manner, finding a solution using quantum states and measurements, and physically implementing the solution. Since quantum mechanics can violate Bell inequalities, quantum solutions to a CDNP problem have advantages over non-quantum solutions.

Abstract: A bit interleaving method involves applying a bit permutation process to bits of a QC-LDPC codeword made up of N cyclic blocks each including Q bits, and dividing the codeword after the permutation process into a plurality of constellation words each including M bits, the codeword being divided into F×N?/M folding sections (N? being a subset of N selected cyclic blocks and being a multiple of M/F), each of the constellation words being associated with one of the F×N?/M folding sections, and the bit permutation process being applied such that each of the constellation words includes F bits from each of M/F different cyclic blocks in a given folding section associated with a given constellation word.

Abstract: Methods, systems, and apparatus for solving cost optimization problems. In one aspect, a method includes receiving data representing a cost optimization problem in a network, wherein i) the network is represented as a graph of nodes and edges, and ii) each edge comprises an associated cost; mapping the data representing the cost optimization problem in a network to a quadratic unconstrained binary optimization (QUBO) formulation of the cost optimization problem, the QUBO formulation comprising multiple variables with values determined by states of respective qubits, wherein each qubit corresponds to a respective edge of the graph of nodes and edges; obtaining data representing a solution to the cost optimization problem from a quantum computing resource; and initiating an action based on the obtained data representing a solution to the cost optimization problem.

Abstract: An integrated circuit includes a processor core configured to perform boot operations; and a microcontroller coupled to a processor core. The microcontroller includes: a set of microcontroller components; and a state machine coupled to the set of microcontroller components. The state machine is configured to perform self-test operations on the set of microcontroller components before the boot operations.

Abstract: A storage system caches, in volatile memory, data read from non-volatile memory. After detecting an uncorrectable error in the data cached in the volatile memory, the storage system replaces the cached data with data re-read from the non-volatile memory and updated to reflect any changes made to the data after it was stored in the non-volatile memory. The storage system can also analyze a pattern in data adjacent to the uncorrectable error and predict corrected data based on the pattern.

Abstract: In accordance with an embodiment, a system includes an oscillator equipped circuit having an oscillator control circuit configured to be coupled to an external oscillator and a processing unit comprising a clock controller. The clock controller includes an interface circuit configured to exchange handshake signals with the oscillator control circuit, a security circuit configured to receive the external oscillator clock signal and configured to select the external oscillator clock signal as the system clock, and a detection block configured to detect a failure in the external oscillator clock signal. Upon detection of the failure, a different clock signal is selected as the system clock and the interface circuit to interrupts a propagation of the external oscillator.

Abstract: The disclosure describes various techniques to control of small angle Mølmer-Sørensen (MS) gates and to handle asymmetric errors. A technique is described that implements a two-qubit calibration circuit with two MS gates, where a parameter ? represents an amount of entanglement of the MS gate. The calibration circuit is run for several values of ? to measure observed parity signals that are direct measurements of the values of ?. Calibration information is generated that describes the relationship between ? and the parity signals, and such calibration information is then provided to arbitrarily calibrate one or more MS gates in a quantum simulation. Another technique is described for using the calibration information in quantum simulations, including for quantum chemistry simulations.

Abstract: A quantum-mechanics station (?-station) and a cloud-based server cooperate to provide quantum mechanics as a service (?aaS) including real-time, exclusive, interactive sessions. The ?-station serves as a system for implementing “recipes” for producing, manipulating, and/or using quantum-state carriers, e.g., rubidium 87 atoms. The cloud-based server acts as an interface between the station (or stations) and authorized users of account holders. To this end, the server hosts an account manager and a session manager. The account manager manages accounts and associated account-based and user-specific permissions that define what actions any given authorized user for an account may perform with respect to a ?-station. The session manager controls (e.g., in real-time) interactions between a user and a ?-station, some interactions allowing a user to select a recipe based on wavefunction characterizations returned earlier in the same session.

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

Abstract: Methods, systems, and apparatus, for totally corrective boosting with cardinality penalization are described. One of the methods includes obtaining initialization data identifying training examples, a dictionary of weak classifiers, and an active weak classifier matrix. Iterations of a totally corrective boosting with cardinality penalization process are performed, wherein each iteration performs operations comprising selecting a weak classifier from the dictionary of weak classifiers that most violates a constraint of a dual of the primal problem. The selected weak classifier is included in the active weak classifier matrix. The primal problem is optimized, and a discrete weight vector is determined. Weak classifiers are identified from the active weak classifier matrix with respective discrete weights greater than a threshold. The regularized risk is optimized, and a continuous weight vector is determined.

Abstract: A hybrid quantum-classical (HQC) computer takes advantage of the available quantum coherence to maximally enhance the power of sampling on noisy quantum devices, reducing measurement number and runtime compared to VQE. The HQC computer derives inspiration from quantum metrology, phase estimation, and the more recent “alpha-VQE” proposal, arriving at a general formulation that is robust to error and does not require ancilla qubits. The HQC computer uses the “engineered likelihood function” (ELF) to carry out Bayesian inference. The ELF formalism enhances the quantum advantage in sampling as the physical hardware transitions from the regime of noisy intermediate-scale quantum computers into that of quantum error corrected ones. This technique speeds up a central component of many quantum algorithms, with applications including chemistry, materials, finance, and beyond.