Abstract: Disclosed are various embodiments related to stacked memory devices, such as DRAMs, SRAMs, EEPROMs, ReRAMs, and CAMs. For example, stack position identifiers (SPIDs) are assigned or otherwise determined, and are used by each memory device to make a number of adjustments. In one embodiment, a self-refresh rate of a DRAM is adjusted based on the SPID of that device. In another embodiment, a latency of a DRAM or SRAM is adjusted based on the SPID. In another embodiment, internal regulation signals are shared with other devices via TSVs. In another embodiment, adjustments to internally regulated signals are made based on the SPID of a particular device. In another embodiment, serially connected signals can be controlled based on a chip SPID (e.g., an even or odd stack position), and whether the signal is an upstream or a downstream type of signal.

Abstract: A memory circuit includes a bias voltage generator, a drive circuit, and a resistive random-access memory (RRAM) device. The bias voltage generator includes a first transistor configured to generate a voltage difference based on a first current and an activation voltage, and is configured to output the activation voltage and a bias voltage based on the voltage difference. The drive circuit is configured to receive the bias voltage and output a drive voltage having a voltage level based on the bias voltage, and the RRAM device is configured to receive the activation voltage and conduct a second current responsive to the drive voltage and the activation voltage.

Abstract: A non-volatile memory includes a memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines, an outer memory cell string including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O). The data I/O circuit includes a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.

Abstract: Disclosed is a power management integrated circuit including dual one-time programmable memory banks and methods for controlling the same. In one embodiment, the power management integrated circuit (PMIC) includes a first one-time programmable (OTP) memory bank; a second OTP memory bank; and access control logic, communicatively coupled to the first OTP bank and the second OTP bank, the access control logic configured to: utilize the first OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is empty, write data to the second OTP memory bank in response to a write request from a host application if the second OTP memory bank is not empty, and utilize the second OTP memory bank for operation of the PMIC upon detecting that the second OTP memory bank is not empty.

Abstract: A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.

Abstract: A new type of two-terminal magnetic memory device, referred to as antiferromagnetic voltage-controlled memory (AVM) device is disclosed. Antiferromagnetic (AFM) materials have zero magnetization, which makes it immune to external magnetic fields and opens to the possibility to implement high-density arrays without dipole coupling between adjacent devices. The AVM device combines a new state variable e.g., Néel vector l in a metallic (or non-metallic) AFM material with an electric-field-induced switching mechanism for writing of information. Utilizing electric fields E via an interfacial voltage-controlled magnetic anisotropy (VCMA) effect is a more efficient writing mechanism. The AVM device implements an antiferromagnetic tunnel junction (AFM-TJ) structure to exhibit high or low resistance states (HR, LR) corresponding to binary logic states of zero (0) or one (1). Both the AVM device structure and methods of writing a signal to the AVM device are disclosed.

Abstract: An apparatus, a method, and a system. The method includes implementing an erase operation on a deck of a superblock, block or subblock of a three-dimensional (3D) non-volatile memory device to obtain an erased deck; applying a dummy read pulse to one or more wordlines (WLs) of a to-be-read deck of the superblock, block or subblock; and implementing, after application of the dummy read pulse, a read operation on one or more memory cells corresponding to the one or more WLs to read data from the one or more memory cells.

Abstract: A method for providing a datum in a receive buffer memory. The method includes storing the datum to be provided in the receive buffer memory, and retrieving an old datum from the receive buffer memory, if the receive buffer memory overflows as a result of storing the datum to be provided.

Abstract: Circuit-protection devices might include first and second circuit-protection units each comprising a first node and a second node, a first field-effect transistor having a first source/drain connected to the first node of the first circuit-protection unit, and a second field-effect transistor having a first source/drain connected to the first node of the second circuit-protection unit, wherein a second source/drain of the first field-effect transistor merges with a second source/drain of the second field-effect transistor.

Abstract: Systems, methods, and apparatuses for temperature-compensated operation of electronic devices are described. For example, an apparatus for performing voltage compensation on a sense amplifier based on temperature may include a sense amplifier control circuit coupled to the sense amplifier to provide a compensation pulse to the sense amplifier, wherein the sense amplifier operates in a voltage compensation phase during the compensation pulse. The apparatus may determine the compensation pulse responsive to a voltage compensation duration signal that is based on the operating temperature of the apparatus. The voltage compensation occurs when there is no activate command immediately before or immediately after so that compensation duration change do not happen during an activate command from the command decoder.

Abstract: A method comprising: performing a first read from an address in a data storage module by using a first read voltage; storing, in a first register, data that is retrieved from the data storage module as a result of the first read; performing a second read from the address by using a second read voltage; storing, in a second register, data that is retrieved from the data storage module as a result of the second read; detecting whether a weak bit condition is present at the address based on the data that is stored in the first register and the data that is stored in the second register; and correcting the weak bit condition, when the weak bit condition is present at the address.

Abstract: A phase change memory (PCM) device including a bottom electrode, a bottom heater over the bottom electrode, a bottom buffer layer over the bottom heater, a PCM region over the bottom buffer layer, a top buffer layer over the PCM region, a top heater over the top buffer layer, and a top electrode over the top heater.

Abstract: Disclosed is a magnetic device including a spin sinker. The magnetic device includes a storage medium, a spin sinker, and a read node. The storage medium receives an in-plane current from outside and generates a self-generated spin current that perpendicularly flows to a charge current, thereby controlling a data structure with the self-generated spin current. The spin sinker receives and attenuates the spin current. The read node measures a magnetoresistance of a data structure through the storage medium. The storage medium is made of a magnetic metal and the spin sinker is made of a magnetic insulating material.

Abstract: A memory macro system may be provided. The memory macro system may comprise a first segment, a second segment, a first WL, and a second WL. The first segment may comprise a first plurality of memory cells. The second segment may comprise a second plurality of memory cells. The first segment may be positioned over the second segment. The first WL may correspond to the first segment and the second WL may correspond to the second segment. The first WL and the second WL may be configured to be activated in one cycle.

Abstract: The present technology relates to an electronic device. A memory controller controls a memory device to efficiently use a storage space of the memory device. The memory controller controlling the memory device includes a cache buffer configured to store data received from a host and output the data to the memory device, and a program mode setting component configured to determine a program mode based on a size of the data output from the cache buffer to the memory device, and output an address and a command according to the determined program mode.

Abstract: A memory device includes a memory array comprising a plurality of wordlines and a regulator circuit selectively coupled to the plurality of wordlines, wherein the regulator circuit is configured to perform a detection routine to sample a load current from a selected wordline of the plurality of wordlines and generate a measured output voltage, wherein the measured output voltage modulates with respect to the load current. The memory device further includes a comparator circuit coupled to the regulator circuit, wherein the comparator circuit is configured to generate a comparison result based on a difference between the measured output voltage and a reference voltage and a local media controller coupled to the comparator circuit, wherein the local media controller is configured to identify a presence of a defect on the selected wordline in response to the comparison result satisfying a threshold condition.

Abstract: Devices and methods include distributing biases for input buffers of a memory device. The devices include multiple input buffers configured to buffer data for storage in the multiple memory banks. The devices also include biasing generation and distribution circuitry configured to generate and distribute biases to the multiple input buffers. The biasing generation and distribution circuitry includes bias voltage generation circuitry and multiple remote resistor stacks each located at a corresponding input buffer of the input buffers and remote from the bias voltage generation circuitry.

Abstract: Some embodiments include an integrated assembly having first and second source/drain regions laterally offset from one another. Metal silicide is adjacent to lateral surfaces of the source/drain regions. Metal is adjacent to the metal silicide. Container-shaped first and second capacitor electrodes are coupled to the source/drain regions through the metal silicide and the metal. Capacitor dielectric material lines interior surfaces of the container-shaped first and second capacitor electrodes, A shared capacitor electrode extends vertically between the first and second capacitor electrodes, and extends into the lined first and second capacitor electrodes. Some embodiments include methods of forming integrated assemblies.

Abstract: A magnetic memory device includes a first electrode, a second electrode, and a layer stack located between the first electrode and the second electrode. The layer stack includes a reference layer, a tunnel barrier layer, a free layer, and a magnetoelectric multiferroic layer including at least one crystalline grain. The magnetization of the magnetoelectric multiferroic layer may be axial, canted, or in-plane. For axial or canted magnetization of the magnetoelectric multiferroic layer, a deterministic switching of the free layer may be achieved through coupling with the axial component of magnetization of the magnetoelectric multiferroic layer. Alternatively, the in-plane magnetization of the magnetoelectric multiferroic layer may be employed to induce precession of the magnetization angle of the free layer.

Abstract: Some embodiments include an integrated assembly having a set of true digit-lines and a set of complementary digit-lines. Each of the complementary digit-lines is comparatively coupled with an associated one of the true digit-lines. A semiconductor substrate is under the true digit-lines. The semiconductor substrate includes semiconductor features which project upwardly from a semiconductor base and which extend along a first direction. Each of the semiconductor features has opposing sidewalls. First source/drain regions are within the semiconductor features and second source/drain regions are within the semiconductor base. The true digit-lines are coupled with the first source/drain regions. Wordlines are along the opposing sidewalls and include gating regions which gatedly couple the first source/drain regions with the second source/drain regions. Storage-elements are coupled with the second source/drain regions. In some embodiments, memory may utilize a 4F2 layout.