Abstract: Embodiments of a Stochastic memristive array (SMA) device based on arrays of voltage-controlled magnetic tunnel junctions (MTJs) are disclosed. The SMA device is based on an array of stochastic (low energy barrier) magnetic tunnel junctions that are connected in parallel which simultaneously exhibits features that include (i) stochasticity and (ii) memristive behavior. The energy barrier of the MJTs may be tuned by an applied voltage (electric field). SMA devices may find applications in emerging computing concepts such as probabilistic computing and memcomputing, among others, providing a pathway towards intelligent hybrid CMOS-spintronic systems.

Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.

Abstract: The present invention relates to an oilfield management system. The oilfield management system comprises: one or more devices for measuring working conditions of oil wells, the one or more devices for measuring working conditions of oil wells are installed on one or more oil wells respectively for measuring working conditions of the one or more oil wells, the working conditions of oil wells at least comprise indicator diagrams of oil wells; one or more remote transmission units, each of the remote transmission units receives the working conditions measured by one or more of the devices for measuring working conditions of oil wells; and server, which determines running status of the one or more oil wells according to the working conditions of oil wells from the one or more remote transmission units; maintenance staff or administrators manage the one or more oil wells according to the running status of the one or more oil wells.

Abstract: A non-volatile memory includes a memory cell region including a first metal pad, a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad, a memory cell array region in the memory cell region including an outer region proximate a first end of the memory cell region and an inner region separated from the first end by the outer region, first and second bit lines in the memory cell region, an outer memory cell string in the memory cell region including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region, and a data input/output (I/O) circuit in the peripheral circuit region including a page buffer circuit that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and connects

Abstract: A memory system includes a memory device and a controller. The controller receives data from a host, allocates buffers after a throttling delay, buffers the data in the buffers, provides the buffered data to the memory device for a write operation, generates a response associated with the write operation, and transmits the response to the host. The controller inserts a throttling delay before allocating the buffers and/or transmitting the response. The throttling delay is determined based on a time elapsed since providing previously buffered data to the memory device and the size of the buffered data. The throttling delay is corrected based on the difference of the number of currently allocated buffers and a buffer reserve threshold.

Abstract: Methods, systems, and devices for phase charge sharing are described. In some memory systems or memory devices, one or more decoders may be used to bias access lines of a memory die. The decoders may transfer voltage or current between a first conductive line of the decoder and a second conductive line of the decoder via a shorting device. Transferring the voltage or current may be performed as part of or in association with an operation (e.g., an activate or pre-charge operation) to access one or more memory cells of the memory die. In some examples, the decoders may transfer voltage or current between a first conductive line of a decoder associated with a first refresh activity and a second conductive line of the decoder associated with a second refresh activity via a shorting device.

Abstract: Provided is a word-line structure including a substrate, a word line, and an epitaxial pattern. The word line is embedded in the substrate. The word line includes a conductive layer, a barrier layer, an insulating layer, and a gate dielectric layer. The barrier wraps a lower portion of the conductive layer. The insulating layer wraps an upper portion of the conductive layer. The gate dielectric layer surrounds the insulating layer and the barrier layer to electrically isolate the barrier layer from the substrate. The epitaxial pattern is disposed between the insulating layer and the substrate and in contact with the substrate. A memory device including the word-line structure and a method of manufacturing the same are also provided.

Abstract: A signal generation circuit is disclosed according to an embodiment of the invention. The signal generation circuit includes a phase control circuit, a bias control circuit and a phase interpolation circuit. The phase control circuit is configured to generate a phase control signal according to a phase adjustment signal. The bias control circuit is configured to generate a bias voltage according to the phase control signal. The phase interpolation circuit is configured to generate a clock signal according to the phase control signal and the bias voltage. The bias voltage is used to adjust a current of the phase interpolation circuit to correct an error of the clock signal.

Abstract: According to one embodiment, a memory device includes first to third interconnects, memory cells, and selectors. The first to third interconnects are provided along first to third directions, respectively. The memory cells includes variable resistance layers formed on two side surfaces, facing each other in the first direction, of the third interconnects. The selectors couple the third interconnects with the first interconnects. One of the selectors includes a semiconductor layer provided between associated one of the third interconnects and associated one of the first interconnects, and gates formed on two side surfaces of the semiconductor layer facing each other in the first direction with gate insulating films interposed therebetween.

Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.

Abstract: The invention relates to a measuring device and a measurement method for the display of a measurement signal connected to the measuring device. The measuring device comprises a measurement-signal input, a measurement-parameter input, a calculation unit and a display unit for the display of calculated statistical signals. The measuring device is set up to display a plurality of statistical signals in parallel on the display unit in real-time.

Abstract: A system for storing and looking up values via hash table is disclosed. The system comprises multiple hash tables, each hash table being associated with a different hashing function and a content addressable memory (CAM). One or more processors receive a request to store a value; generate hashes of the value via each of the hashing functions; determine whether there exists at least one hash table that has a vacancy for the value; and if the determination is positive, insert the value in one of the at least one hash tables having the vacancy, and if the determination is negative, insert the value in the CAM. The processors also receive a request to look up a value; determine whether any of the hash tables or the CAM contain the value; and return the determination of whether the any of the plurality of hash tables or the CAM contain the value.

Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.

Abstract: Programmable devices and methods for fabricating the programmable devices are described. In an example, a method for fabricating a programmable device can include bonding a UV light source to a computer chip by flip-chip mounting the UV light source to the computer chip. The UV light source can be configured to emit UV light towards a UV erasable area of the computer chip to perform UV erasing on the computer chip. The method can further include bonding a carrier to the computer chip by flip chip mounting the computer chip to the carrier using a second array of bond pads.

Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory may include memory elements. Each of the memory elements comprises: a selection element layer in which a first dopant is doped in an insulating material; and a variable resistance layer in which a second dopant is doped in the insulating material. A diffusivity of the second dopant in the insulating material is greater than a diffusivity of the first dopant in the insulating material.

Abstract: A refresh processing method, apparatus, and system, and memory controllers are provided, to improve memory access efficiency. The refresh processing apparatus includes a plurality of memory controllers that are in one-to-one correspondence with a plurality of memory spaces. Any first memory controller in the plurality of memory controllers is configured to: receive N first indication signals and N second indication signals that are output by N memory controllers other than the first memory controller, where N is greater than or equal to 1; and determine a refresh policy of a first memory space based on at least one of the following information: the N first indication signals, the N second indication signals, and refresh indication information of the first memory space.

Abstract: A semiconductor device includes a buffer control circuit and an operation control circuit. The buffer control circuit generates an enable signal based on a self-refresh signal and to generate an end control signal and a supply control signal from a first internal chip selection signal during a self-refresh operation. The operation control circuit generates a frequency information signal from an internal command/address signal when an update signal is inputted during a mode register write operation, adjusts a shift amount based on the frequency information signal when the supply control signal is inputted during the mode register write operation, and generates an internal write command according to the adjusted shift amount during a read-modify-write operation in synchronization with an internal clock signal after generating an internal read command.

Abstract: An MRAM bitline write control circuit including an MRAM array of a plurality of MTJ cells. Each MTJ cell is connected to a bitline between a bitline transfer gate and a transfer device. Each transfer device is connected to a sourceline and a sourceline transfer gate. A master bitline is connected to each bitline transfer gate. A first bitline control transistor is connected to VDD and to a source follower transistor that is connected to the master bitline and a gate connected to a write 0 bias voltage. A second bitline control transistor is connected to VSS and to the master bitline. A selected MTJ cell is biased to write a 0 when the transfer device, the bitline transfer gate and the source line transfer gate, associated with the selected MTJ cell, are enabled and the first bitline control transistor is enabled to connect the source follower transistor to VDD.

Abstract: An apparatus includes a programming circuit configured to supply a program pulse to increase a threshold voltage of a memory cell. The apparatus also includes a sensing circuit configured to determine that the threshold voltage of the memory cell satisfies a trigger threshold voltage in response to the program pulse. The apparatus further includes a damping circuit configured to increase a voltage of a bit line connected to the memory cell after initiation of and during a second program pulse in response to the threshold voltage of the memory cell satisfying the trigger threshold voltage, the second program pulse being sent by the programming circuit.

Abstract: Various implementations described herein are directed to a device having memory circuitry with a core array of bitcells. The device may include write assist circuitry having passgates coupled to the bitcells via bitlines. The passgates may include a first passgate coupled to the bitcells via a first bitline and a second passgate coupled to the bitcells via a second bitline, and a gate of the second passgate may be coupled to the first bitline.