Abstract: Methods and associated structures for utilizing write-back cache management modes for local cache memory of disk drives coupled to a storage controller while maintaining data integrity of the data transferred to the local cache memories of affected disk drives. In one aspect hereof, a state machine model of managing cache blocks in a storage controller cache memory maintains blocks in the storage controller's cache memory in a new state until verification is sensed that the blocks have been successfully stored on the persistent storage media of the affected disk drives. Responsive to failure or other reset of the disk drive, the written cache blocks may be re-written from the copy maintained in the cache memory of the storage controller. In another aspect, an alternate controller's cache memory may also be used to mirror the cache blocks from the primary storage controller's cache memory as additional data integrity assurance.

Abstract: A directory structure for a sparsely filled data container comprises a linked list, doubly linked list, skip list, or other non-fully populated list technique. One or more hierarchical levels of such lists may be used for sparsely filled directories. The directory structure may be converted to a conventional look-up table directory by reconstructing the directory when the directory becomes populated to certain point.

Abstract: The present invention relates to a method and apparatus for dumping memory. More particularly a computer-implemented method of saving at least some data within volatile storage to non-volatile storage when a computer system panics is described. The method includes the steps of: the computer system defining a specified portion of volatile storage (1) containing data to be saved as a dump device (2), rebooting (8) the computer system without affecting the data within the dump device, and the computer system copying (12) the data in the dump device to non-volatile storage (13). A reboot of the computer system after copying the data to non-volatile storage is not necessary for the computer system to begin (14) normal operation.

Abstract: A disk drive is disclosed comprising a disk, a head actuated over the disk, and a history array for storing a plurality of history records, wherein each history record having a history range identifying a range of sector addresses proximate the sector address of a host command. As new host commands are received, the sector address of each host command is compared to the history records in the history array. A counter is adjusted in response to each comparison, and an operating mode of the disk drive is configured into a new operating mode if the counter exceeds a threshold, wherein the configuring includes adjusting at least one of the history range and the threshold relative to the new operating mode.

Abstract: Apparatus and method for providing information to a cache module, the apparatus includes: (i) at least one processor, connected to the cache module, for initiating a first and second requests to retrieve, from the cache module, a first and a second data unit; (ii) logic, adapted to receive the requests and determine if the first and second data units are mandatory data units; and (iii) a controller, connected to the cache module, adapted to initiate a single fetch burst if a memory space retrievable during the single fetch burst comprises the first and second mandatory data units, and adapted to initiate multiple fetch bursts if a memory space retrievable during a single fetch burst does not comprise the first and the second mandatory data units.

Abstract: Circuits and methods of rearranging the order of data in a memory having asymmetric input and output ports are disclosed. According to one embodiment, a method comprises steps of providing an input port of a memory having an input width and output port having an output width which is different than the input width. A plurality of data words are received at the input of the memory, wherein each data word has a width corresponding to the input width. The order of the plurality of input data words is rearranged; and an output word based upon the rearranged data words and having a width corresponding to the output width is generated. Various circuits and algorithms for implementing the methods are also disclosed.

Abstract: A logical table has a layered structure formed of a higher layer logical table arranged on a memory and a lower layer logical table arranged on a disk and stores where each part of a physical region corresponding to each part of a virtual volume is located, a physical table has a layered structure formed of a higher layer physical table arranged on the memory and a lower layer physical table arranged on the disk and stores a state of assignment of each part of a physical region, and a controller copies a part or all of the lower layer logical table and the lower layer physical table into the memory to conduct management of virtual volume.

Abstract: The present invention provides a method and apparatus for increased efficiency for translation lookaside buffers by collapsing redundant translation table entries into a single translation table entry (TTE). In the present invention, each thread of a multithreaded processor is provided with multiple context registers. Each of these context registers is compared independently to the context of the TTE. If any of the contexts match (and the other match conditions are satisfied), then the translation is allowed to proceed. Two applications attempting to share one page but that still keep separate pages can then employ three total contexts. One context is for one application's private use; one of the contexts is for the other application's private use; and a third context is for the shared page. In one embodiment of the invention, two contexts are implemented per thread. However, the teachings of the present invention can be extended to a higher number of contexts per thread.

Abstract: A data processing system according to the invention comprises a processor (P) and a memory hierarchy. The highest ranked level therein is a cache coupled to the processor. The memory hierarchy comprises a higher ranked cache (C1) having a cache controller (CC1) operating according to a write allocate scheme, and a lower ranked cache (C2) is coupled to the higher ranked cache (C1) having a cache controller (CC2). The size of the higher ranked cache is smaller than the size of the lower ranked cache. Both caches (C1, C2) administrate auxiliary information (V1, V2) indicating whether data (D1, D2) present therein is valid. The line size of the lower ranked cache (C2) is an integer multiple of the line size of the higher ranked cache (C1). The auxiliary information (V1) in the higher ranked cache (C1) concerns data elements (D1) at a finer granularity than that in the lower ranked cache (C2).

Abstract: A method and apparatus for processing a bi-directional dataflow are disclosed which permits the transparent movement of data from one processor to another via a shared memory fabric which is connected with both processors. This permits the incoming data of a first processor to be utilized by a second processor thereby freeing that processor from having to handle incoming data. Further, the second processor can handle outgoing data exclusively, freeing the first processor from having to handle outgoing data. In this way, each direction of a bi-directional dataflow may be handled by the maximum capability of a bi-directional capable processing device. The shared memory may comprise a plurality of banks of synchronous dynamic random access memory (SDRAM) devices, and may be used to store packet data in a network.

Abstract: A flash memory system including one or more flash memory devices; the flash memory devices are partitioned into multiple units, at least a first unit and a second unit. A mechanism which allocates the units in combination as a super-unit, reserves at least a portion of a first unit field required for managing the super-unit in the first unit and the mechanism reserves at least a portion of a second unit field required for managing the super-unit in the second unit. Preferably, the first unit field and the second unit field are different unit fields, or the first unit field and the second unit field are the same unit field. Preferably, the flash memory device each support at least two planes, and the first unit and the second unit each belong to a different plane. Alternatively, there are two flash memory devices, and the first unit and the second unit each belong to a different flash memory device.

Abstract: A storage system have a plurality of control modules which control a plurality of disk storage devices. In order to read/write system information even when problems arise in paths with the plurality of disk devices, and moreover to output log data even upon occurrence of an abnormality in the control module, a plurality of control modules which control a plurality of disk storage devices, each have a built-in system disk device unit which stores log data. In equalization processing, log data of one control module is stored in a system disk of another installed control module. Even when an abnormality occurs in the one control module, log data of the one control module can be output by the other control module.

Abstract: Techniques are provided for performing transaction-aware caching of metadata in an electronic file system. A mechanism is described for providing transaction-aware caching that uses a cache hierarchy, where the cache hierarchy includes uncommitted caches associated with sessions in an application and a committed cache that is shared among the sessions in that application. Techniques are described for caching document metadata, access control metadata and folder path metadata. Also described is a technique for using negative cache entries to avoid unnecessary communications with a server when applications repeatedly request non-existent data.

Abstract: A centralized memory allocation system utilizes write pointer drift correction. The memory stores data units. The memory controller receives a write request associated with a data unit and stores the data unit in the memory. The memory controller also transmits a reply that includes an address where the data unit is stored. The control logic receives the reply and determines whether the address in the reply differs from an address included in replies associated with other memory controllers by a given address range. When this occurs, the control logic performs a corrective action to bring an address associated with the memory controller back within a defined range.

Abstract: In a buffering apparatus for digital data for temporarily storing input data and then outputting, a memory apparatus is provided with a plurality of storage areas assigned consecutive identification numbers. A partition designation unit generates an instruction for partitioning the plurality of storage areas. An area partitioning unit partitions the plurality of storage areas in the memory apparatus at least into a first area and a second area in accordance with the generated instruction for partitioning and uses the first area as a buffer area, the first area including storage areas with consecutive identification numbers. A partition designation unit generates an instruction for partitioning that designates a border between the first area and the second area.

Abstract: A storage system includes an application server that provides an application composed of a plurality of programs, a plurality of first volumes that store data that the programs use, and a plurality of second volumes set in pair states where replicas of the plurality of first volumes are stored. A program for managing the storage system controls a computer to execute the procedures of: identifying any one of the plurality of programs; identifying a first volume that the identified program uses; obtaining every second volume set in a pair state with the first volume; and summarizing the first volume and the obtained second volume for the identified program.

Abstract: Methods and apparatus for migrating a logical object. In one embodiment, a migration is performed by automatically determining the source location(s) of the logical object, moving the data stored therein to a target location while maintaining the availability of the data at the source location to an application program, and automatically servicing access requests from the application program at the target location after moving the data. In another embodiment, a migration is performed by automatically provisioning target location(s) to store a logical object, moving the data in the logical object to the target location(s) while maintaining its availability to an application program, and automatically servicing access requests from the application program at the target location after moving the data.

Abstract: A storage system that may include one or more memory devices, a memory interface device corresponding to one or more of the memory devices, which are organized in sections, a section controller, and a switch. The switch is capable of reading a data request including a data block identifier and routing the data request and any associated data through the switch on the basis of this data block identifier, such that a data request may be routed to a memory section. The section controller, in response, determines the addresses in the memory devices storing the requested data, and it transfers these addresses to those memory devices storing the requested data.

Abstract: An interleaver for use with transform processors provides an address generator allowing for implementation using a reduced memory foot print, and permitting interleaving of an input sequence while minimizing latency.

Abstract: A disk array system of the type that each controller has an independent and dedicated cache. The disk array system can change control of a desired volume between desired controllers without suspending the system. When volumes are taken over between controllers, a switch-source controller de-stages data of a subject volume on the data cache to a storage subject disk to maintain the disk content reflection (coherency). Even if each controller has an independent and dedicated cache, a desired volume can be taken over between desired controllers without suspending the system. Each controller has a configuration manager which stores the controller number of a switch-destination controller to allow automatic volume take-over and automatic control by the original controller.