Abstract: A circuit is disclosed for preventing the erasing and programming of a nonvolatile memory device during power up and power down transitions. A power supply generator incorporating an n-channel device and a w-channel device in a wired-or configuration is coupled to a programming voltage Vpp and to a circuit voltage Vcc, and generates a node voltage Vpwr which is the greater of Vpp-Vtn and Vcc-Vtw. Vtn is the gate threshold voltage of the n-channel device, while Vtw is the gate threshold voltage of the w-channel device. The node voltage Vpwr is coupled to a reference voltage generator which provides a reference voltage, a protecting voltage, and a biasing voltage for a Vcc comparator and a Vpp comparator. The Vcc comparator and the Vpp comparator compare Vref with the output of a Vcc divide-by-two circuit and a Vpp divide-by-five cirucit, respectively.

Abstract: According to one embodiment of the present invention, a magnetic bubble memory module comprising a flexible printed circuits substrate (FPC3), on which a magnetic bubble memory chip (CHI) is mounted and electrically connected, with interconnecting patterns (9a) electrically connecting the chip (CHI) with external connecting leads, terminals or pins as well as bias coil winding (BIC2) for applying bias field to the chip (CHI), thereby reducing the number of components as well as fabricating steps because of the formation of the bias coil (BIC2) with the printed circuits substrate (FPC3).

Abstract: A semiconductor memory device having a redundant memory cell group selectable by a redundant decoder operable by a small power consumption is disclosed. The redundant decoder comprises a plurality of address program circuits which store address of a defective memory cell or cells and a control circuit for enabling the address program circuits when at least one defective memory cell is present and disenabling the address program circuits when no defective memory cell is present.

Abstract: A process for transferring Bloch lines formed in a magnetic wall of a magnetic domain and a magnetic memory apparatus for recording/reproducing information in utilizing Bloch lines formed in the magnetic wall of the magnetic domain as a information carrier are disclosed. The process comprises steps of forming a positive or negative magnetic charge area in the magnetic wall, thereby attaching a Bloch line to the area, and moving the magnetic charge area, thereby moving the Bloch line. The apparatus comprises a memory substrate having a stripe-shaped magnetic domain, a way to write Bloch lines in the magnetic wall of the stripe-shaped magnetic domain according to input information, a way to read the Bloch lines so stored to reproduce the information in the form of electric signals and a way to apply a rotating magnetic field parallel to the plane of the memory substrate, to the stripe-shaped magnetic domain, to move the Bloch lines along the magnetic wall.

Abstract: A method of transferring Bloch lines present in a domain wall of a magnetic domain formed in a thin magnetic firm, includes cyclically forming asymmetrical potential wells along the domain wall in order to locate the Bloch lines at predetermined positions of the domain wall, and applying a pulsed magnetic film to shift the Bloch lines from a predetermined potential well to another potential well. In a magnetic memory for recording information using Bloch lines as an information carrier, a memory substrate has a stripe magnetic domain defined by a domain wall along which asymmetrical potential wells are cyclically formed to stabilize the Bloch lines along the domain wall. The Bloch lines are written in the domain wall in accordance with input information, the Bloch lines so formed are read out, and the read-out Bloch lines are converted into an electrical signal.

Abstract: A programmable device has a cell formation region having rows and columns of programmable cells arranged in a matrix arrangement, a real cell region within the cell formation region and constituted by the programmable cells which are to be actually programmed, a test bit region within the cell formation region and including a number of rows of the programmable cells so as to include all kinds of the programmable cells within the real cell region, and a test word region within the cell formation region and including a number of columns of the programmable cells so as to include all kinds of the programmable cells within the real cell region. All of the programmable cells within the real cell region can essentially be tested by testing the programmable cells within the test bit region and the test word region.

Abstract: According to one embodiment of the present invention, a magnetic bubble memory module comprising a flexible printed circuits substrate (FPC3), on which a magnetic bubble memory chip (CHI) is mounted and electrically connected, with interconnecting patterns(9a) electrically connecting the chip (CHI) with external connecting leads, terminals or pins as well as bias coil winding (BIC2) for applying bias field to the chip (CHI), thereby reducing the number of components as well as fabricating steps because of the formation of the bias coil (BIC2) with the printed circuits substrate (FPC3).

Abstract: An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

Abstract: A memory which senses output signals from a selected memory cell during a read cycle using a non-address transition detection apparatus. The memory has a plurality of memory cells which provide signals to a pair of bit lines when selected. An input circuit drives word lines and select a bit line pair of a memory cell located at the intersection of a selected word line and a selected bit line pair. The memory cell outputs bit line signals which are sensed by a combination of a differential amplifier, a level shifter, and a transconductance amplifier, and are thereafter output and presented externally at a logic state representative of a differential current at outputs of the transconductance amplifier. The combination sensing apparatus and a method for constructing such an apparatus decrease access time significantly over a prior art memory using address transition detection.

Abstract: SRAM device having a power supply voltage control circuit capable of preventing the failure of memory cells used for a long period of time, without lowering a power supply voltage is disclosed. The SRAM device includes a plurality of word lines, a plurality of pairs of bit lines, a plurality of memory cells each coupled between a word line and each pair of bit lines, and a power supply regulating stage coupled to each memory cell, for decreasing a supply voltage delivered to each memory cell when an external power supply voltage exceeds a specified voltage level, and delivering the external power supply voltage to each memory cell when the external power supply voltage does not exceed the specified voltage level. If an external power supply voltage is lower than a voltage level Vc, the supply voltage is supplied as a power source of the memory cell.

Abstract: In typical MOS integrated circuit devices, the level of the back-bias voltage which is generated by a built-in back-bias generation circuit and is supplied to a semiconductor substrate is changed by an undesirable leakage current flowing through the semiconductor substrate. The leakage current is not constant. Instead, it becomes relatively small when a main circuit formed on the semiconductor substrate such as a dynamic RAM is not operative, and relatively great when such a circuit is operative. To reduce the change of the back-bias voltage resulting from the change of the leakage current, a back-bias voltage generation circuit is provided which has output capacity of a plurality of levels. Its output capacity is increased in response to an operation control signal of the main circuit.

Abstract: An IC card such as cash card is disclosed. The IC card has a RAM, a control circuit for controlling access to the RAM, and a power supply circuit receiving outside energy and supplying power to the RAM and the control circuit. A first voltage detector produces a starting output when supply voltage of the power exceeds a predetermined first reference voltage. A second voltage detector produces a control signal when the supply voltage exceeds a predetermined second reference voltage, which is higher than the first reference voltage. An AND gate is provided to produce a RAM control signal for operating the RAM when the starting signal and the control signal are applied thereto.

Abstract: A static random access memory device is comprised of a write mode detector for detecting a signal state transition of a write enable signal changing to an active state, an input data transition detector for detecting a transition of the input data supplied from exterior, during a continuation of the active state of the write enable signal, an address signal transition detector for detecting a transition of an externally applied address signal during an active state of the write enable signal, a power down timer for generating a pulse signal with a predetermined pulse width in response to any of the detecting signals outputted from the write mode detector, input data transition detector, and address signal transition detector, a gate circuit for permitting the output data from a row decoder to be transferred to memory cells during a period that the power down timer generates a pulse signal, and for inhibiting that data transfer during a period that the power down timer rests, and a write circuit control circui

Abstract: A FIFO memory device facilitates transfer of data between a host CPU and a peripheral device in one of a number of modes. In one mode, the FIFO memory device functions as two FIFO memories, one for passing data from the host CPU to the peripheral device, and one for passing data to the host CPU from the peripheral device. In another mode, the FIFO memory device functions as a single FIFO which facilitates passing data from the host CPU to the peripheral device or from to peripheral device to the host CPU. The FIFO includes two RAMs addressed by a set of address counters. Of importance, the host CPU can bypass the address counters to directly address each RAM, thereby reading data from or writing data into either RAM regardless of the state of the address counters.

Abstract: A variable length shift register comprises a memory cell array (1) having memory cells arranged in a matrix of row and columns, a variable length ring pointer (2) responsive to a bit length selecting signal for sequentially activating a single row in the memory cell array in a recirculated manner within a predetermined constant range, an input buffer (4) for writing data into a memory cell of the activated row, and an output buffer (5) for reading out data from a memory cell of the activated row.

Abstract: A dual-port memory having an on-chip color register for storage of input data for use in multiple write cycles is disclosed. The color register is written to during a special cycle, which is enabled by a special function pin in conjunction with the write enable and transfer enable function pins, each of which have their logic state latched in during the row address strobe signal. A second type of special cycle causes a multiplexer to select the contents of the color register, rather than the latched data state of the data input terminals, for the data to be written to the selected memory cells. The use of the color register may be used in conjunction with a mask register, where the writing of certain input/outputs in inhibited. In addition, a block write feature may be incorporated with the color register so that, in another type of special cycle, multiple columns per input/output can be simulaneously written with the contents of the color register.

Abstract: In a serial input-output circuit comprising a memory device (15) for memorizing an input serial bit sequence as memorized bit groups, each consisting of a predetermined number of parallel bits, first and second bidirectional shift registers (21, 22) are serially connected through a ring connection (24, 25). A storing arrangement (35-37) is connected to the respective shift registers and directly to the memory device for bit parallel storage of the parallel bits of a selected one of the memorized bit groups in a selected one of the shift registers. An output serial bit sequence is produced from one of the shift registers selectively forwardly and backwardly as regards time relative to the input serial bit sequence. The storing arrangement may comprise a register selector (35) and first and second bit parallel connections (36, 37).

Abstract: The rate of single event upset in a memory cell due to energetic particle hits on a p-channel device is reduced by a pair of active devices in the cross-coupling between a pair of inverters. The active devices are controlled by voltages internal to the memory cell such that writing into the cell is not slowed significantly. Additionally, means such as a resistor or transistor are disclosed which reduce the rate of single event upset due to energetic particle hits on a n-channel device.

Abstract: A memory cell is disclosed which operates in two stable states and where an asymmetry in current through the cell is required to change the state of the cell. The cell includes a current compensating device that supplies current under ionizing radiation in a direction that is opposite to that required to write into the cell.

Abstract: An address counter (2) counts the clock pulses sequentially to provide a count value as an address signal to a coincidence detecting circuit (3) and decoder (4). The coincidence detecting circuit (3) compares delay data applied from a delay data generating circuit (8) with the address signal and applies a reset signal to the address counter (2) when they coincide with each other. The address counter (2) repeats sequentially the above-mentioned operation in response to the reset signal after the count of address is reset to a predetermined value. The decoder (4) specifies a memory cell comprised in a memory device for performing a reading and writing operation in response to the address signal. The data output circuit (6) and the data input circuit (5) perform the reading and writing operation sequentially to the specified memory cell in response to the control signal outputted from the control circuit (7). As a result, the input data previously written is read and outputted with a delay.