Abstract: An output memory circuit device for and method of providing protection to an integrity of data stored in an external memory circuits during an output operation utilizing the data. Control means selectively controls activation of an external memory to an active state and an inactive back-up state, and obtains data from the external memory circuit during times corresponding to the active state. Storage circuit receives and temporarily stores data supplied by the control circuit and processing circuit receives and processes data fed from the storage circuit and outputs processed data to an output circuit. The control circuit selectively controls an activation of the external memory circuit to the inactive back-up state during times when receiving and processing is conducted to receive and process data fed from the storage circuit and output processed data to the output circuit.

Abstract: Random access memory unit having a plurality of test modes, which is constructed as an integrated circuit and which does not include specific input/output pins to define and to command the passage to test mode. This unit is equipped with means (1) for detecting whether a predefined sequence of logic signals, which is not contained, within a set of sequences which are normally used, but the voltages of which are nevertheless included within the range of voltages which are specified for such signals, is supplied to certain inputs (CE, WE, AO), and for placing the unit in-test mode when such a sequence has been detected. In order to define the nature of the test to be performed, address input terminals, (A1-A8) of the unit are connected to a test mode decoding circuit (2), in which the data applied to the said input terminals are used as data defining the nature of the test to be performed.

Abstract: In a Bloch line memory device, information corresponds to the presence or absence of a Bloch line pair present in the magnetic wall of a stripe magnetic domain. Reading of information is effected by converting the presence and absence of a Bloch line pair into the presence and absence of a magnetic bubble domain. The conversion is effected such that, after the stripe magnetic domain has been shrunk in such a manner that no Bloch line is present therein, a magnetic field for chopping off the stripe magnetic domain is applied to the shrunken portion. Thus, when a Bloch line is present at an end portion of the stripe magnetic domain, the stripe magnetic domain is chopped off to form a magnetic bubble domain, whereas, when no Bloch line is present at the end portion of the stripe magnetic domain, the stripe magnetic domain is not chopped off and therefore no magnetic bubble domain is formed. Whether the magnetic bubble domain is present or absent is processed as information.

Abstract: A highly integrated memory features increased reading speed and writing speed. A sense circuit for this memory including a memory cell array having a plurality of memory cells each of which including at least one insulated gate field effect transistor, and a plurality of data lines to which the memory cells are connected. The memory also includes an address selection mechanism which is capable of selecting a memory cell out of a plurality of memory cells and connecting it to the data line. A sense amplifier a mechanism which is connected to the data line and amplifies a voltage according to the data of a memory cell. A common line (input/output line) is connected to the data lines, via a column switch, where the selection depends upon a column address. A main amplifier is connected to the common line (input/output line), and has at least a mechanism for stabilizing the voltage of the common line (input/output line) and an amplifying mechanism.

Abstract: A semiconductor memory device having an improved arrangement of bit lines which can operates stably, is disclosed. The memory device comprises a plurality of first bit line pairs, a plurality of second bit line pairs, and a plurality of sense amplifiers, a control circuit for connecting either of the first bit line pairs and the second bit line pairs to the sense amplifiers, and is featured in that the first and second bit line pairs are alternately arranged in parallel one by one.

Abstract: An analog dynamic memory circuit comprises a time delay element with a variable delay time feedback loop and a time delay element control device which changes the delay time of the time delay element every time when an analog signal circulates in the feedback loop. This analog dynamic memory circuit prevents or avoids superposition of noise signals which have the same phase in the loop circuit, with the result that amplification of noise and tuned waves in the circuit is prevented.

Abstract: A method for the addressing of redundant elements of an integrated circuit memory is disclosed. This memory comprises an array of row memory elements and column memory elements, respectively addressable by row addresses and column addresses, at least one battery of fuses to store the address of a faulty element of the memory. The method consists:for one battery, in associating said battery with a row/column address pair;in memorizing, through the blowing of certain fuses in the battery after the testing of a memory element, the address either of a column element if the faulty element is a column element or that of a row element if the faulty element is a row element;and in enabling only the row addresses when the stored address is that of a row element or only the column addresses when the stored address is that of a column element, to address either a row redundant element or a column redundant element.

Abstract: A semiconductor dynamic RAM provided with an I/O load (5) rendered inactive during a writing cycle comprises a monostable multivibrator (16) for receiving a read/write indicating signal W for indicating reading and writing data from and into a memory cell (2) and outputting a signal W having a shorter duration than that of the signal W at a down edge of the signal W as a trigger. The output signal W of the monostable multivibrator (16) is supplied as a control signal for rendering the I/O load (5) inactive.

Abstract: A serially addressing type memory integrated circuit with an improved shift register operable at a high speed and fabricated on a reduced area of chip, is disclosed and featured in that the shift register has a plurality of first stages connected in cascade and arranged from a first location to a second location and a plurality of second stages connected in cascade and arranged from the second location to the first location and the first and second stages are alternately arranged one by one, and that an access detection circuit for indicating an access to an approximately center of serial addresses is connected to one of the first and second stages near the second location.

Abstract: A self-testing and self-repairing memory system is presented as well as a method for using it and a method for making it. This memory system is constructed from memory chips that have passed an abbreviated wafer probe test. After the memory system is assembled, it tests itself to locate defective memory cells. The memory system may decide to correct these defective memory cells or it may decide to correct them using an error correction code engine. This memory system tests itself during field use to locate defective memory cells. Once these defective memory cells are located, the memory system uses the error correction code engine to correct these defective memory cells. When the error correction code engine becomes overburdened with defective memory cells, then the memory system replaces these defective memory cells.

Abstract: A hologram transducer using the Faraday effect in magnetic bubble devices for recording and reproducing the amplitude and phase distributions over a section of a beam of coherent light is disclosed. The transducer spatially modulates the intensity, by using linear polarization, and the phase, by using circular polarization, of light transmitted through a magnetic bubble device. Using linear polarization and a single magnetic bubble domain to traverse in a sequence the possible storage positions in the magnetic bubble device, the transducer samples at each of these positions the intensity of the transmitted light. Using in addition a coherent reference beam of light to interfere with the light being measured, the transducer samples the phase in the half range of 0 through .pi. radians at these positions. Further, using a quarter cycle phase shift in the reference beam, the transducer resolves the phase values over the full range of 0 through 2.pi. radians.

Abstract: A memory cell array (61) comprises a plurality of three-transistor type memory cells (10) arranged in a plurality of rows and columns. A plurality of pairs of write bit lines (WB1, WB2) and a plurality of read bit lines (RB) are provided corresponding to each column of the memory cell array (61). The plurality of write word lines (WWL) and the plurality of read word lines (RWL) are provided corresponding to each row of the memory cell array (61). Information is written to memory cells (10) in odd rows through the respective one write bit lines of the pairs of write bit lines (WB1, WB2), and information is written to memory cells (10) in even rows through the respective other write bit lines of the pairs of write bit lines (WB1, WB2). A sense amplifier (30) is connected to each of the pairs of write bit lines (WB1, WB2). At the time of write operation, refresh operation is performed by the sense amplifier (30) with respect to memory cells (10) in non-selected columns.

Abstract: A static semiconductor memory device having an improved write circuit which can perform a write operation at a high speed is disclosed. The memory device comprises a plurality of memory cells each having a flip-flop holding a first level and a second level lower than the first level and a write circuit for operatively generating a write data signal which is applied to a selected one of the memory cells, the write data signal selectively assuming a low level of write data signal which is lower than the second level.

Abstract: A single chip semiconductor memory device having an arithmetic circuit to conduct plural kinds of arithmetic operations and a mask control circuit for inhibiting a substantial change in data in memory irrespective of the operations of the arithmetic circuit when it is brought into a masking state. The semiconductor memory device takes a preset operation mode for receiving from the outside a control signal for the arithmetic circuit and the mask control circuit. This control signal for the arithmetic circuit and the mask control circuit, which is given to the semiconductor memory device when in the preset operation mode, is latched in the semiconductor memory device until the device is brought again into the preset operation mode.

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of word lines; a row pre-decoding unit responsive to a row address signal, outputting a plurality of row pre-decode signals with units of a group having signals of a number corresponding to a combination of each logic level of a predetermined plurality of bits of the row address signal; a row pre-decode wiring for transmitting the plurality of row pre-decode signals; a row main decoder responsive to one signal in each group of the plurality of row pre-decode signals, carrying out a main decoding for selecting one of the plurality of word lines; a pseudo row decoder having substantially same electrical characteristics as the row main decoder, carrying out a simulation of the main decoding in response to the plurality of row pre-decode signals output on row pre-decode wiring; and a word line driver for driving a word line selected by the row main decoder to a predetermined level.

Abstract: A volatile storage circuit for latching data is disposed outside a non-volatile memory array. Before a bulk erase of the memory array, some of the data items contained therein are transferred to and held by the storage circuit. The data items thus saved are rewritten to the non-volatile memory array after the bulk erase, or alternatively, on the basis of control data items transferred to the storage circuit, only regions designated by these data items are subjected to the bulk erase. Thus, in case of a bulk erase of an EEPROM, some of the stored data items can be preserved, so as to prevent illicit use of and maintain the integrity of the preserved data. Also the testing time of the data rewritten to the memory array is reduced because of the elimination of the need to test the memory area containing the preserved data in that only the integrity of the memory area containing data sourced externally need be tested.

Abstract: An interconnection system for transferring either electrical energy in the form of power and data signals or both is disclosed. Capacitive coupling devices are shown connected to a memory device such as an erasable programmable read only memory chip, in a form suitable for use in a smart data entry card. The capacitive coupling devices employ a dielectric medium having a relatively high dielectric constant due to the orientation of the crystals of the dielectric medium. Barium Titinate having a dielectric constant of 18,000 in the direction of the crystal axis is used. Only small bearing pressures sufficient to wipe contaminants from the exposed contact pads are required.

Abstract: An economical circuit arrangement permits disruption, during a nuclear event or single event upset, of operation in portions of a bubble memory system and in a computer connected thereto while maintaining integrity of data stored in the bubble memory. Only critical portions of the bubble support circuits are radiation hardened, and a nonstop logic circuit is provided to continue operation during a nuclear event and to conclude any memory access cycles already in progress at the beginning of the event. Spurious (ionization induced) drive pulses are distinguished from actual pulses. A nuclear event detector generates an output pulse during the event and a delay is provided in a path of the pulses in the critical circuit portions. The delay is greater than the duration of the output pulse of the detector so that pulses arriving after the detector pulse are ignored.

Abstract: A method of reconditioning an electrically programmable semiconductor read only memory cell which includes heating the cell to a temperature which is sufficiently high and for a sufficient duration so that the Write/Erase window is re-opened.

Abstract: A memory which contains a global data line pair and a plurality of loads for the global data line pair distributed thereon. The global data lines run the length of the memory, and are connected to a set of arrays distributed along the global data lines, of which each array provides a voltage on the global data lines when selected. The first load is located above the first array and the last is located below the last array. Other global data line loads are placed between consecutive arrays. In a read mode of operation a pair of loads associated with each array is enabled when a corresponding array is selected. Placement of the loads in this manner decreases an access time considerably.