Abstract: A magnetoresistive element comprises a novel iPMA cap layer on a surface of a recording layer to induce a giant interfacial perpendicular magnetic anisotropy (G-iPMA) of the recording layer and a method of making the same. The recording layer comprises a first free layer immediately contacting to the tunnel barrier layer and having a body-centered cubic structure with a (100) texture, and a second free layer having a body-centered cubic structure with a (110) texture or a face-centered cubic structure with a (111) texture, and a crystal-breaking layer inserted between the first free layer and the second free layer.

Abstract: The present invention proposes a self-emission type display and a repairing method thereof. The self-emission type display includes a carrier substrate and a light-emitting element. The carrier substrate includes a first electrode, a second electrode, and a plurality of repairing electrodes. The first electrode has a plurality of first strip portions connected to a first level. The second electrode has a plurality of second strip portions connected to a second level. The first electrode is separated from the second electrode, and the first level is different from the second level. The repairing electrodes are electrically insulated from the first electrode and the second electrode. The light-emitting element is disposed on the carrier substrate and has a first connecting portion and a second connecting portion. The first connecting portion is electrically connected to the first level through the first strip portions.

Abstract: A semiconductor device includes a power transistor in a semiconductor substrate portion, where the semiconductor substrate portion includes a central portion and a kerf, components of the power transistor are arranged in the central portion, and the central portion has a thickness d. The semiconductor device also includes a support element disposed over a main surface of the central portion, where the support element has a smallest lateral extension t at a side adjacent to the main surface of the semiconductor substrate portion and a height h, where 0.1×h?d?4×h and 0.1×h?t?1.5×h.

Abstract: A device may include a lead frame, where the lead frame includes a central portion, and a side pad, the side pad being laterally disposed with respect to the central portion. The device may further include a thyristor device, the thyristor device comprising a semiconductor die and further comprising a gate, wherein the thyristor device is disposed on a first side of the lead frame on the central portion. The device may also include a positive temperature coefficient (PTC) device electrically coupled to the gate of the thyristor device, wherein the PTC device is disposed on the side pad on the first side of the lead frame; and a thermal coupler having a first end connected to the thyristor device and a second end attached to the PTC device.

Abstract: The invention relates to a method for manufacturing mirrors with saturable semiconducting absorptive material, which includes: depositing a saturable semiconducting absorptive material (205) onto a growth substrate (200) in order to form a structure; depositing at least one metal layer onto the structure such as to form a first mirror (211); and depositing a heat-conductive substrate (212) onto the metal layer by electrodeposition through an electrically insulating mask (312), allowing the selective deposition of the thermally conductive substrate, in order to predefine the perimeter of the mirrors with saturable semiconducting absorptive material.

Abstract: A system may include at least one sensor, at least one machining device, and a computing device. The computing device may be operable to control the at least one sensor to inspect at least a portion of a coversheet of a dual walled component to generate dimensional surface data for the at least a portion of the coversheet and compare the dimensional surface data to surface model data. The comparison may indicate portions of the coversheet that include additional material. The computing device also may be operable to generate a compromise surface model based on the comparison between the dimensional surface data and the surface model data and control the at least one machining device to machine the dual walled component based on the compromise surface model to remove the additional material.

Abstract: A semiconductor memory device includes, for example, a substrate having a fin having a web portion extending from the substrate and a first overhanging fin portion extending outward from the web portion and spaced from the substrate, the fin comprising a source/drain region in the web portion of the fin, a first source/drain region in the first overhanging fin portion, an isolation material surrounding the web portion and disposed under the first overhanging fin portion of the fin, an upper surface of the isolation material being below an upper surface of the fin, a first gate disposed over the fin between the source/drain region in the web portion of the fin and the first source/drain region in the first overhanging fin portion of the fin, and a capacitor operably electrically connected to the first source/drain region in the first overhanging fin portion.

Abstract: A chip package including a substrate that has a first surface and a second surface opposite thereto is provided. The substrate includes a chip region and a scribe line region that extends along the edge of the chip region. The chip package further includes a dielectric layer disposed on the first surface of the substrate. The dielectric layer corresponding to the scribe line region has a through groove that extends along the extending direction of the scribe line region. A method of forming the chip package is also provided.

Abstract: Electrical fuse (eFuse) and resistor structures and methods of manufacture are provided. The method includes forming metal gates having a capping material on a top surface thereof. The method further includes protecting the metal gates and the capping material during an etching process which forms a recess in a dielectric material. The method further includes forming an insulator material and metal material within the recess. The method further includes forming a contact in direct electrical contact with the metal material.

Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.

Abstract: A lens casing in an LED illumination apparatus hermetically housing LED elements is cooled. The LED illumination apparatus includes a tubular lens casing, an LED holding part mounting the LED elements thereon, and a base part to which the lens casing is coupled. The base part has a concave part for housing the LED holding part, and the lens casing is coupled to the base part, thereby hermetically sealing the internal space of the lens casing. The base part has support columns protruding into a space outside the LED illumination apparatus and supporting a fan device. The fan device makes taken-in air collide with the base part and exhausts the air through the window parts each formed by adjacent support columns and the side of the frame of the fan device and the side of the base part that face each other as upper and lower frames thereof.

Abstract: A display apparatus includes a substrate including a display area, a peripheral area surrounding the display area, a function-adding area, of which at least a portion is surrounded by the display area, and a detour area disposed between the display area and the function-adding area. The display apparatus includes a plurality of pixel circuits disposed in the display area. A plurality of driving lines are electrically connected to the pixel circuits and extend in a direction in the display area. A first detour line is disposed in the detour area and is electrically connected to a first driving line. A second detour line is disposed in the detour area. The second detour line is electrically connected to a second driving line and is disposed in a different layer from the first detour line.

Abstract: A fan-out semiconductor package includes: a first interconnection member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface; an encapsulant encapsulating at least portions of the first interconnection member and the inactive surface of the semiconductor chip; and a second interconnection member disposed on the first interconnection member and the active surface of the semiconductor chip.

Abstract: An optical sensor includes a substrate, light emitting units for emitting light with different wavelengths, and a photodetector. The substrate has at least one receiver for containing these light emitting units and a slot for containing the photodetector. A light guide structure of the optical sensor can be the receiver with a specific design, so that the light emitted by the light emitting units can be reflected towards a central axis of the photodetector. Thus, when at least one of the light emitting units emits light onto an object, the photodetector can receive the light reflected from the object.

Abstract: A transistor having a narrow bandgap semiconductor source/drain region is described. The transistor includes a gate electrode formed on a gate dielectric layer formed on a silicon layer. A pair of source/drain regions are formed on opposite sides of the gate electrode wherein said pair of source/drain regions comprise a narrow bandgap semiconductor film formed in the silicon layer on opposite sides of the gate electrode.

Abstract: A recessed high voltage metal oxide semiconductor (MOS) transistor is provided for use in a two-terminal memory cell. The two-terminal memory cell can include a resistive switching device connected to the recessed MOS transistor. The recessed MOS transistor provides for an increased channel length relative to the transistor size in comparison to a traditional MOS transistor. This allows for a decreased memory cell size while maintaining comparable electrical parameters (threshold voltage, channel length, and leakage) than would otherwise be possible. The recessed MOS transistor can be made as either a NMOS or PMOS device using n-type or p-type materials respectively, where the channel, or inversion layer, is formed by electrons (NMOS) or holes (PMOS) between the source and drain in the transistor.

Abstract: A semiconductor device has a resistance change element that is high in the holding resistance of a low resistance (On) state while securing a memory window. In a resistance random access memory including selection transistors and resistance change elements coupled in series to the selection transistors, the resistance change element uses a lower electrode that applies a positive voltage when being transited to a high resistance (Off) state, an upper electrode that faces the lower electrode, and a resistance change layer that is sandwiched between the lower electrode and the upper electrode and that uses an oxide of transition metal. The resistance change layer contains nitrogen. The concentration of nitrogen on the lower electrode side is higher than that on the upper electrode side. The nitrogen in the resistance change layer exhibits a concentration gradient continuously declined from the lower electrode side to the upper electrode side.

Abstract: According to an embodiment, a semiconductor memory device comprises first wiring lines, second wiring lines, and first variable resistance elements. The first wiring lines are arranged in a first direction and have as their longitudinal direction a second direction intersecting the first direction. The second wiring lines are arranged in the second direction and have the first direction as their longitudinal direction. The first variable resistance elements are respectively provided at intersections of the first wiring lines and the second wiring lines. In addition, this semiconductor memory device comprises a first contact extending in a third direction that intersects the first direction and second direction and having one end thereof connected to the second wiring line. The other end and a surface intersecting the first direction of this first contact are covered by a first conductive layer.

Abstract: A material stack of a synthetic anti-ferromagnetic (SAF) reference layer of a perpendicular magnetic tunnel junction (MTJ) may include an SAF coupling layer. The material stack may also include and an amorphous spacer layer on the SAF coupling layer. The amorphous spacer layer may include an alloy or multilayer of tantalum and cobalt or tantalum and iron or cobalt and iron and tantalum. The amorphous spacer layer may also include a treated surface of the SAF coupling layer.

Abstract: A vertical junction field effect transistor (JFET) is supported by a semiconductor substrate that includes a source region within the semiconductor substrate doped with a first conductivity-type dopant. A fin of semiconductor material doped with the first conductivity-type dopant has a first end in contact with the source region and further includes a second end and sidewalls between the first and second ends. A drain region is formed of first epitaxial material grown from the second end of the fin and doped with the first conductivity-type dopant. A gate structure is formed of second epitaxial material grown from the sidewalls of the fin and doped with a second conductivity-type dopant.