Abstract: A semiconductor package includes an interconnect component surrounded by a molding compound. The interconnect component comprises a first RDL structure. A second RDL structure is disposed on the interconnect component. A plurality of first connecting elements is disposed on the second RDL structure. A polish stop layer covers a surface of the interconnect component. A plurality of second connecting elements is disposed on and in the polish stop layer. At least one semiconductor die is mounted on the second connecting elements.

Abstract: A power semiconductor module includes a module housing and a circuit carrier having a dielectric insulation carrier and an upper metallization layer applied onto an upper side of the dielectric insulation carrier. A semiconductor component is arranged on the circuit carrier. The power semiconductor module also has an electrically conductive terminal block connected firmly and electrically conductively to the circuit carrier and/or to the semiconductor component. The terminal block has a screw thread that is accessible from an outer side of the module housing. A method for producing such a power semiconductor module is also provided.

Abstract: A package, able to encapsulate at least one component, forming a closed cavity of Faraday cage type having side walls resting on a base and that are surmounted by a cover, wherein at least one of the side walls includes exterior electrical connection elements linked electrically to the interior of the cavity, the exterior connection elements able to interconnect with an exterior circuit such that the side wall faces the exterior circuit when the exterior connection elements are interconnected with the circuit.

Abstract: A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

Abstract: A power semiconductor module is produced by: providing an electrically conductive terminal block having a screw thread, a connecting conductor having first and second sections, a module housing, a circuit carrier having a dielectric insulation carrier and an upper metallization layer on an upper side of the insulation carrier, and a semiconductor component; fitting the semiconductor component on the circuit carrier; producing a firm and electrically conductive connection between the terminal block and the connecting conductor at the first section; producing a material-fit and electrically conductive connection between the circuit carrier or the semiconductor component and the connecting conductor at the second section; and arranging the terminal block and the circuit carrier fitted with the semiconductor component on the module housing so the semiconductor component is arranged in the module housing and the screw thread is accessible from an outer side of the module housing.

Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.

Abstract: A power semiconductor device is disclosed. In one example, the device includes a semiconductor body coupled to a first load terminal structure and a second load terminal structure. An active cell field is implemented in the semiconductor body. The active cell field is surrounded by an edge termination zone. A plurality of first cells and a plurality of second cells are provided in the active cell field. Each first cell includes a first mesa, the first mesa including: a first port region and a first channel region. Each second cell includes a second mesa, the second mesa including a second port region. The active cell field is surrounded by a drainage region that is arranged between the active cell field and the edge termination zone.

Abstract: A wiring substrate includes a flexible insulation substrate, a first wiring layer formed on an upper surface of the insulation substrate, a second wiring layer formed on a lower surface of the insulation substrate, and through wiring bonded to the first wiring layer and the second wiring layer and formed in a through hole extending through the first wiring layer, the insulation substrate, and the second wiring layer. The through wiring includes a projection that extends along a lower surface of the second wiring layer located outside the through hole. An upper surface of the through wiring is flush with an upper surface of the first wiring layer.

Abstract: A microelectronic package including a passive microelectronic device disposed within a package body, wherein the package body is the portion of the microelectronic package which provides support and/or rigidity to the microelectronic package. In a flip-chip type microelectronic package, the package body may comprise a microelectronic substrate to which an active microelectronic device is electrically attached. In an embedded device type microelectronic package, the package body may comprise the material in which the active microelectronic device is embedded.

Abstract: Electronic power device comprising: an active layer comprising several lateral and/or semi-lateral components for which the electrodes are located on a front face of the active layer; an interconnection structure comprising several conducting portions to which component electrodes are connected, and located in contact with these electrodes extending parallel to the active layer; a support comprising a front face on which electrically conducting tracks are located, and in which: the interconnection structure is located between the active layer and the support, the conducting portions being placed in contact with the conducting tracks, or the active layer is placed between the interconnection structure and the support, the conducting portions comprising parts extending next to the active layer and connected to the conducting tracks.

Abstract: A package comprising an at least partially electrically conductive chip carrier, a first transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, and a second transistor chip comprising a first connection terminal, a second connection terminal and a control terminal, wherein the first transistor chip and the second transistor chip are connected to form a half bridge, and wherein the second connection terminal of the first transistor chip is electrically coupled with the first connection terminal of the second transistor chip by a bar section of the chip carrier extending between an exterior edge region of the first transistor chip and an exterior edge region of the second transistor chip and maintaining a gap laterally spacing the first transistor chip with regard to the second transistor chip.

Abstract: A fan-out semiconductor package includes a first connection member having a through-hole, a semiconductor chip with connection pads on its active surface disposed in the through-hole and a first encapsulant encapsulating at least portions of the first connection member and the semiconductor chip. A second connection member is disposed below the first connection member and the semiconductor chip. A first heat dissipation member is formed in the first connection member. A component package is disposed on the fan-out semiconductor package and includes a wiring substrate connected to the first connection member through connection terminals, electronic components disposed on the wiring substrate, a second encapsulant encapsulating at least portions of the electronic components, and a second heat dissipation member formed in the wiring substrate. At least one of the electronic components is connected to the first heat dissipation member through the second heat dissipation member.

Abstract: A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality of power semiconductor switches arranged thereon, and at least one second conductive substrate electrically coupled to the first conductive substrate. A first terminal is electrically coupled to the first conductive substrate. The power module also includes a second substrate including a third conductive substrate having a second plurality of power semiconductor switches arranged thereon, and at least one fourth conductive substrate electrically coupled to the third conductive substrate. The third conductive substrate is electrically coupled to the second conductive substrate. A second terminal is electrically coupled to the fourth conductive substrate.

Abstract: A device and method utilizes interconnecting layers separated by an insulating layer. A layered structure comprises a first and a second layer of electrically conductive material, and a third layer of electrically insulating material between them. A via trench is fabricated that extends from the second layer through the third layer into the first layer, a surface on the first layer of electrically conductive material forming a bottom surface of the via trench. An ink-jetting set-up for a mixture of liquid carrier and nanoparticles of conductive material is formed, and a specific process period is determined. Capillary flow of nanoparticles to peripheral edges of an ink-jetted blob of said mixture is induced. The mixture is ink-jetted into a blob on the via trench; the layered structure is heated to evaporate the liquid carrier. The interconnection element is higher at a certain point than between opposing side walls.

Abstract: A semiconductor device includes: a semiconductor die having first and second opposite surfaces, a die pad having the first surface of the semiconductor die attached thereon, an electrically conductive ground pad at the second surface of the semiconductor die, a device package coupled with the semiconductor die with the ground pad lying between the semiconductor die and the package, and ground wiring or tracks for the semiconductor die between the second surface of the semiconductor die and the ground pad. A further ground connection may be provided between the ground pad at the second surface of the semiconductor die and the die pad having the semiconductor die attached thereon.

Abstract: A three-dimensional (3D) integrated circuit (IC) die is provided. In some embodiments, a first IC die comprises a first semiconductor substrate, a first interconnect structure over the first semiconductor substrate, and a first hybrid bond (HB) structure over the first interconnect structure. The first HB structure comprises a HB link layer and a HB contact layer extending from the HB link layer to the first interconnect structure. A second IC die is over the first IC die, and comprises a second semiconductor substrate, a second HB structure, and a second interconnect structure between the second semiconductor substrate and the second HB structure. The second HB structure contacts the first HB structure. A seal-ring structure is in the first and second IC dies. Further, the seal-ring structure extends from the first semiconductor substrate to the second semiconductor substrate, and is defined in part by the HB contact layer.

Abstract: Some embodiments of the present disclosure provide a semiconductive device. The semiconductive device includes a first conductive layer and a second conductive layer above the first conductive layer. The second conductive layer includes a first portion and a second portion protruding from the first portion. A via structure is under the second conductive layer and on top of the first conductive layer. The via structure is substantially aligned vertically with the second portion.

Abstract: The present invention provides a semiconductor memory device, includes at least one static random access memory (SRAM) cell, wherein the SRAM cell includes a first pick-up node, and a dielectric oxide SRAM (DOSRAM), disposed in a first dielectric layer and disposed above the SRAM cell when viewed in a cross section view, wherein the DOSRAM includes an oxide semiconductor filed effect transistor (OSFET) and a capacitor, a source of the OSFET is electrically connected to the first pick-up node of the SRAM cell through a via structure, and at least parts of the first dielectric layer are disposed between the source of the OSFET and the via structure, and the capacitor is disposed above the OSFET and electrically connected to a drain of the OSFET when viewed in the cross section view.

Abstract: A semiconductor device having a repairable penetration electrode is provided. The semiconductor device having the repairable penetration electrode includes first and second signal transfer regions including main penetration electrodes penetrating a substrate, and a repair region including a spare penetration electrode penetrating the substrate. The first and second signal transfer regions are spaced apart from each other. The repair region is disposed between the first and second signal transfer regions. The first and second signal transfer regions share the repair region such that the spare penetration electrode of the repair region is substituted for a defective main penetration electrode of the first and second signal transfer regions.

Abstract: A semiconductor package and or method of fabricating a semiconductor package may be provided. The semiconductor package may include a package substrate. The semiconductor package may include a first semiconductor die coupled to the package substrate by first interconnectors. The semiconductor package may include a second semiconductor die coupled to the first semiconductor die by second interconnectors. The second semiconductor die may be coupled to the substrate.