Abstract: A monopole-streetlight assembly includes: an elongate monopole having lower and upper ends; a module configured for mounting of telecommunications antennas; the module including an upper plate and a central spine having an upper end that extends above the upper plate; an adapter having a lower sleeve that receives the upper end of the spine and a flange that extends radially outwardly from the sleeve; and a luminaire unit having an arm having a base, the base being secured to the adapter flange, and further having a luminaire mounted opposite the base.

Abstract: Three elements of a first (¼) wavelength element and a second (¼) wavelength element which have a length of (¼) wavelength at an arbitrary frequency designated in advance and a half-wavelength element which has a length of a half-wavelength at the arbitrary frequency are arranged in a three-orthogonal state where those are orthogonal to each other, one end portion of the first (¼) wavelength element is joined to one end portion of the second (¼) wavelength element, another end portion of the second (¼) wavelength element is joined to one end portion of the half-wavelength element, a feeding point for antenna power feeding is arranged in a position in which the one end portion of the first (¼) wavelength element is joined to the one end portion of the second (¼) wavelength element, and an antenna is formed as a one-wavelength twisted Z-shaped three-orthogonal dipole antenna.

Abstract: A multichip system includes a plurality of processor chips each having one or more cores and a plurality of antenna module for establishing interchip wireless communication. Each antenna module is disposed on a chip. At least one antenna module includes an antenna element array and a Butler matrix. The antenna element array includes n circular patch antenna elements for 360° end-fire scanning, where n is equal to 4 or a multiple thereof. The Butler matrix has n/4 submatrices. Each submatrix include two input 90° hybrids each having two outputs and two inputs for selectively receiving signals from a transceiver. The Butler matrix also includes two output 90° hybrids each having two outputs and two inputs. The two inputs of each output 90° hybrid are coupled to an output of different ones of the input 90° hybrids. Each output of the output 90° hybrids are coupled to a different antenna element.

Abstract: A structure includes first to fourth conductors. The first conductor extends along a second plane including a second direction and a third direction intersecting with the second direction. The second conductor faces the first conductor along a first direction intersecting with the second plane and extends along the second plane. The third conductor capacitively connects the first conductor and the second conductor. The fourth conductor is electrically connected to the first conductor and the second conductor, and extends along a first plane including the first direction and the third direction. In the third conductor, a surface facing an opposite direction of the fourth conductor in the second direction is covered by a resist layer that includes a dielectric body. In the resist layer, a thickness above a central portion of the third conductor is lower than a thickness above a peripheral edge portion of the third conductor.

Abstract: A clock gating circuit includes a NOR logic gate, a transmission gate, a cross-coupled pair of transistors, and a first transistor. The NOR logic gate is coupled to a first node, and receives a first and a second enable signal, and outputs a first control signal. The transmission gate is coupled between the first and a second node, and receives the first control signal, an inverted clock input signal and a clock output signal. The cross-coupled pair of transistors is coupled between the second node and an output node, and receives at least a second control signal. The first transistor includes a first gate terminal configured to receive the inverted clock input signal, a first drain terminal coupled to the output node, and a first source terminal coupled to a reference voltage supply. The first transistor adjusts the clock output signal responsive to the inverted clock input signal.

Abstract: An antenna device includes a first conductor corresponding to communication in a first frequency band, a ground conductor that faces the first conductor, and a second conductor that is disposed between the first conductor and the ground conductor, faces the first conductor and the ground conductor, and has a power supply point. The second conductor is disposed so as to face one end side of the first conductor in an upper-lower direction of the first conductor. The first conductor has a slot disposed at a position facing the other end side opposite to the second conductor, the slot corresponding to communication in a second frequency band that is different from the first frequency band.

Abstract: An example mount may include a strap (or any other type of clamping mechanism) engaging with an external surface of an antenna. The strap may be connected to a strap base with a canted wall also engaging with the external surface of the antenna. The engagement of the canted wall may be through an abutment of the canted wall against the corresponding external surface of the antenna at a single point or along a single line. Because the entirety of the canted wall does not have to be flush with the corresponding external surface of the antenna, the mount can couple to any kind of antenna form factor, such as curved antennas and antennas with imperfections and protrusions.

Abstract: A metrocell antenna includes a plurality of linear arrays of first frequency band radiating elements, a first enclosure that includes a first of the linear arrays of first frequency band radiating elements mounted therein, a second enclosure that includes a second of the linear arrays of first frequency band radiating elements mounted therein, a third of the linear arrays of first frequency band radiating elements mounted within one of the first and second enclosures, a first RF port that is mounted through the first enclosure and a first blind-mate connector that provides an electrical connection between the first enclosure and the second of the linear arrays of first frequency band radiating elements that is mounted in the second enclosure.

Abstract: An asymmetrical I/O structure is provided. In one embodiment, the asymmetrical I/O structure comprises a first power supply node connected to a first voltage, a second power supply node connected to a second voltage, a pull-up unit and a pull-down unit which are connected between the first power supply node and the second power supply node. The first voltage is higher than the second voltage. A node between the pull-up unit and the pull-down unit is connected to an I/O node. The pull-up unit comprises one or more pull-up transistors, and the pull-down unit comprises one or more pull-down transistors. The number of the pull-up transistors is different from the number of the pull-down transistors.

Abstract: Radiating elements include a first and second dipole arms that extend along a first axis and that are configured to transmit RF signals in a first frequency band. The first dipole arm is configured to be more transparent to RF signals in a second frequency band than it is to RF signals in a third frequency band, and the second dipole arm is configured to be more transparent to RF signals in the third frequency band than it is to RF signals in the second frequency band. Related base station antennas are also provided.

Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

Abstract: In an embodiment, an integrated circuit includes: a voting circuit including N scan flip-flops, where N is an odd number greater than or equal to 3, and where the N scan flip-flops includes a first scan flip-flop and a second scan flip-flop, where an output of the first scan flip-flop is coupled to a scan input of the second scan flip-flop; a scan chain including the N scan flip-flops of the voting circuit, and third and fourth scan flip-flops, the scan chain configured to receive a scan enable signal; and a scan enable control circuit configured to control a scan enable input of the first or second scan flip-flops based on the scan enable signal and based on a scan input of the third scan flip-flop or an output of the fourth scan flip-flop.

Abstract: An electronic device is provided. The electronic device includes a plurality of main device antennas, a switch, and a processor. The switch enables at least one of the main device antennas. The processor is electrically connected to the switch and controls the switch to switch the enabled main device antenna based on a usage status of the electronic device.

Abstract: A load control device for controlling power delivered from an AC power source to an electrical load may comprise a thyristor, a gate current path, and a control circuit. The control circuit may be configured to control the gate current path to conduct a pulse of gate current through a gate terminal of the thyristor to render the thyristor conductive at a firing time during a half-cycle of the AC power source. The control circuit may operate in a first gate drive mode in which the control circuit renders the gate current path non-conductive after a pulse time period from the firing time. The control circuit may operate in a second gate drive mode in which the control circuit maintains the gate current path conductive after the pulse time period during the half-cycle.

Abstract: According to one aspect, an integrated antenna and filter unit, IAFU, is provided. The IAFU includes a filter portion including at least one filter configured to filter RF signals to generate filtered RF signals and a plurality of filter pins configured to output filtered RF signals, and an antenna portion securable to the filter portion where the antenna portion includes a PCB including a plurality of conductor traces each mateable with a corresponding one of the plurality of filter pins to electrically couple the plurality of filter pins directly to corresponding ones of the plurality of conductor traces on the PCB, and a plurality of antennas securable to the PCB where the plurality of antennas are electrically coupled to the plurality of conductor traces.

Abstract: A method of manufacturing an antenna using a radome (10) comprising a front portion (30) and a rear portion (20), the front and rear portions (20, (30) configured to define an interior cavity in which an antenna arrangement is received, the method comprising placing an antenna panel on an inside of one of the front and rear portions, and bringing the portions together, whereby the front portion (30) includes a peripheral channel region (31) configured to contain an adhesive sealant (60) and receive a peripheral edge (21) of the rear portion (20) that is partially submerged in the adhesive sealant (60) before it cures. Additional mechanical fastening clip engagement members (23; 33) are provided inside both the front and rear portions (20; 30) that engage with one another and mechanically secure the radome front and rear portions (20; 30) to each other, in addition to the adhesive joint provided by the adhesive sealant (60) once cured.

Abstract: Radiating elements include a conductive patch having first and second slots that each extend along a first axis and third and fourth slots that each extend along a second axis that is perpendicular to the first axis, a feed network that includes first through fourth feed lines, each feed line crossing a respective one of the first through fourth slots, and a conductive ring that at least partially surrounds the periphery of the conductive patch and that encloses each of the first through fourth slots.

Abstract: The technology relates to a system on chip (SoC). The SoC may include a plurality of network layers which may assist electrical communications either horizontally or vertically among components from different device layers. In one embodiment, a system on chip (SoC) includes a plurality of network layers, each network layer including one or more routers, and more than one device layers, each of the plurality of network layers respectively bonded to one of the device layers. In another embodiment, a method for forming a system on chip (SoC) includes forming a plurality of network layers in an interconnect, wherein each network layer is bonded to an active surface of a respective device layer in a plurality of device layer.

Abstract: The present disclosure describes a strand mount. The strand mount includes a hanging bracket configured to be secured to a cable strand, two or more mounting plates, each mounting plate configured such that a small cell antenna can be mounted thereto, and two or more transition brackets securing the two or more mounting plates to the hanging bracket. The transition brackets and mounting plates are adjustable to allow for directional and/or omni-directional mounting of the small cell antennas to the strand mount. Strand mount assemblies are also described herein.

Abstract: A vehicle antenna includes a conductor plate, a radiator plate facing the conductor plate, a feeding portion located on a same side as the conductor plate with respect to the radiator plate, a connection conductor connecting the feeding portion and the radiator plate, and a first element and a second element arranged away from each other on both sides in a vehicle-width direction of a vehicle with respect to the radiator plate, wherein the radiator plate is arranged at an inclination of equal to or less than ±15 degrees with respect to a vertical plane perpendicular to a horizontal plane.