Abstract: A multi-stage analog-to-digital converter (ADC) suitable for low power applications, such as glucose monitoring, may be required to digitize a slow-moving signal. As such, a multi-stage ADC must be versatile. Accordingly, the multi-stage ADC can be configured to operate at different bandwidths and resolutions through the use of ADC stages that can be enabled or disabled in an exchange between resolution and speed. Each ADC stage digitizes an input signal (e.g., a voltage or a current) using an analog comparison to access a lookup table for a digital signal that represents the input signal at a particular accuracy. Unlike other multi-stage approaches, the digitization is asynchronous (i.e., requires no clock) and can provide simplicity, speed, and low-power operation to the multi-stage ADC.

Abstract: A direct-digital receiver architecture is configured to make maximal use of the dynamic range of its analog to digital converter (ADC). The receiver includes an analog frontend that applies a variable gain factor to the analog input signal, a gain level unit that determines the variable gain factor by monitoring the digital signal that is output by the ADC, a gain scaling unit that determines a digital scale factor according to the determined gain factor, and a gain factor multiplier that multiplies the digital signal by the scale factor to produce a scaled digital signal, said multiplying being time aligned with the variable gain factor. The receiver further includes a digital signal processing train that is cognisant of the dynamic range of the ADC, variable gain factor and the digital scale factor for the time domain sample being processed.

Abstract: Systems and methods for low power sample rate conversion are based on a noise shaping technique. A sample rate conversion circuit includes a clock synchronization circuit configured to receive an input sample sequence at a first sample rate and generate a valid sample sequence that is sampled at a second sample rate different from the first sample rate. The valid sample sequence may include valid samples from a registered sequence sampled at an oversampled rate greater than the first sample rate with invalid samples in the registered sequence being excluded from the valid sample sequence. The sample rate conversion circuit also includes a noise shaping circuit coupled to the clock synchronization circuit and configured to encode the valid sample sequence into a noise-shaped output sequence at the second sample rate by suppressing quantization noise from the valid sample sequence.

Abstract: Method and apparatus for nonlinear signal processing include mitigation of outlier noise in the process of analog-to-digital conversion and adaptive real-time signal conditioning, processing, analysis, quantification, comparison, and control. Methods, processes and apparatus for real-time measuring and analysis of variables include statistical analysis and generic measurement systems and processes which are not specially adapted for any specific variables, or to one particular environment. Methods and corresponding apparatus for mitigation of electromagnetic interference, for improving properties of electronic devices, and for improving and/or enabling coexistence of a plurality of electronic devices include post-processing analysis of measured variables and post-processing statistical analysis. Methods, processes and apparatus for secure communications include low-power communications and physical-layer steganography.

Abstract: A sigma-delta modulator includes an N-bit quantization circuit that generates a stream of N-bit code words and a feedback signal path with an N-bit DAC circuit, having a non-ideal operation due to mismatch error, that converts the stream of N-bit code words to generate a feedback signal. A digital DAC copy circuit provides a digital replication of the N-bit DAC circuit. The digital replication accounts for the non-ideal operation of the N-bit DAC circuit 126 due to mismatch error, and converts the stream of N-bit code words to generate a stream of P-bit code words, where P>N, that are functionally equivalent to the feedback signal output from the N-bit DAC circuit.

Abstract: An electronic device configured to perform polar coding is described. The electronic device includes a bit pattern generator (3403) configured to successively perform a bit pattern generation process over a series (t=?n/w?) of clock cycles; and a counter (c, 4203), operably coupled to the bit pattern generator (3403) and configured to count a number of successive bit pattern generation sub-processes over the series (t=?n/w?) of clock cycles. The bit pattern generator (3403) is configured to: provide a successive sub-set of (w) bits from a bit pattern vector (bk,n) in each successive t=?n/w? clock cycle; where the bit pattern vector comprises n bits, of which ‘k’ bits adopt a first binary value and n?k bits adopt a complementary binary value.

Abstract: Antenna technology includes an antenna oscillator and a planar antenna. The antenna oscillator has a plate-like structure and includes a first resonance part and a second resonance part connected to the first resonance part. The first resonance part and the second resonance part are provided with a first resonance window and a second resonance window, respectively. The first resonance window and the second resonance window have different effective sizes and the antenna oscillator is further provided with a connecting slit.

Abstract: Circuits and methods for minimizing charge losses due to negative transient voltage at summing terminals of an analog to digital converter (ADC) are disclosed. The ADC is coupled to a multi-bit digital to analog converter (DAC) at the summing terminals. The ADC and the DAC include PMOS and NMOS transistors whose timing are controlled to reduce charge losses. The PMOS transistors are turned ON before the NMOS transistors. Also, the PMOS transistor of the ADC is turned ON at a slower rate than the PMOS transistors of the DAC.

Abstract: A method for analog-to-digital conversion with reconfigurable function mapping for acceleration of calculating an activation function of a neural network system includes determining, by a shared circuit, a set of voltage intervals using digital bits in a look-up table to define a shape of the activation function being mapped. The shared circuit determines a set of most significant bits (MSBs) for each voltage interval by storing additional bits in the look-up table corresponding to each voltage interval entry. Further, each of several per-neuron circuits determines whether its accumulated input voltage is in a received voltage interval, and if so, causing the set of MSBs to be stored. Each of the per-neuron circuits determines a set of least significant bits (LSBs) by performing a linear interpolation over the voltage interval. The set of MSBs and the set of LSBs are output as a result of the activation function with analog-to-digital conversion.

Abstract: An apparatus including analog-to-digital conversion (ADC) circuitry is disclosed. The apparatus includes a plurality of comparators susceptible to offset variation and a shuffler circuit configured to shuffle input sources to the respective comparators. Feedback circuitry is also included and is configured and arranged with the ADC circuitry to detect offset variation in the outputs of each comparators for the shuffled inputs, relative to outputs of the plurality of comparators and compensate for the offset variation in the comparators based on the offset differences between the respective comparators.

Abstract: In an antenna, the outer conductor is formed of a first linear conductor, the first linear conductor having a length corresponding to one wavelength of a right-handed circularly polarized wave and circularly extended from a first feed point to a second feed point. The inner conductor is disposed inside the outer conductor and formed of a second linear conductor, the second linear conductor being different from the first linear conductor and having a length determined based on one wavelength of a left-handed circularly polarized wave. The inner conductor has a starting point of the second linear conductor connected to the first feed point and has an end point of the second linear conductor kept free from connection at a location inside the outer conductor, and causes current to flow in a direction opposite to the current flow in the outer conductor.

Abstract: Accordingly, embodiments of the present invention provide a method and apparatus for low-latency, low-power dissipation analog-to-digital conversion. A SAR ADC is implemented using internal signal attenuation, after the signal being sampled, to convert accuracy into speed, allowing higher clock frequency and therefore smaller latency. Some embodiments of the low-latency, low-power dissipation analog-to-digital converters described herein are particularly well-suited to industrial motor control applications, such as analog-to-digital converters that convert relatively high amplitude signals to control motors of robotic or automated industrial manufacturing systems and devices. The reduced latency data conversion of the ADCs allows motor control systems to quickly respond to unanticipated stimulus, which is critical for certain applications, such as robots operating in noisy and unpredictable environments.

Abstract: In general, systems, methods and computer readable media for data record compression using graph-based techniques are provided herein.

Abstract: Systems and methods for stream-based compression include an encoder of a first device that may receive an input stream of bytes including a first byte preceded by one or more second bytes. The encoder may determine to identify a prefix code for the first byte. The encoder may select a prefix code table using the one or more second bytes. The encoder may identify, from the selected prefix code table, the prefix code of the first byte. The encoder may generate an output stream of bytes by replacing the first byte in the input stream with the prefix code of the first byte. The encoder may transmit the output stream from the encoder of the first device to a decoder of a second device. The output stream may have a fewer number of bits than the input stream.

Abstract: An antenna includes first and second feed points spaced apart at a same side of a device main body, and a first grounding point in a receiving area. The first and second feed points and the first grounding point are respectively electrically connected with a first contact point at a first frame, a second contact point at a second frame, and a third contact point at the first frame and a fourth contact point on the main body. An electrical connection body including the first feed point, the first and third contact points, the first grounding point, and the fourth contact point constitutes a first antenna. An electrical connection body including the second feed point, the second contact point, and junction point of the second frame and the main body constitutes a second antenna. The first grounding point is adjacent to the second antenna.

Abstract: A time-multiplexed group of MAC circuits for a machine learning application is provided in which at least one MAC circuit in the time-multiplexed group also functions as a capacitive-digital-to-analog converter (CDAC) within a successive approximation analog-to-digital converter (ADC). A comparator in the ADC is shared by the time-multiplexed group of MAC circuits.

Abstract: A device for monitoring voltage in a battery-operated system, the device including: a ladder selector configured to select between a first resistive ladder and a second resistive ladder; the first resistive ladder includes: a first string of resistors coupled between a sensing input node and a first node of the ladder selector; and a first set of transistors configured to tap intermediate nodes of a set of resistors in the first string of resistors; the second resistive ladder includes: a second string of resistors coupled between the sensing input node and a second node of the ladder selector; and a second set of transistors configured to tap intermediate nodes of a set of resistors in the second string of resistors; and wherein a selected transistor in one of the first set of transistors or the second set of transistors is turned on, and non-selected transistors of the first set of transistors and the second set of transistors are turned off to set a threshold voltage for a sensing output node.

Abstract: An imaging device for improving the determining speed of a comparator and reducing power consumption. The comparator imaging device includes a differential input circuit that operates with a first power supply voltage, the differential input circuit outputs a signal when an input signal is higher than a reference signal in voltage, and a positive feedback circuit that operates with a second power supply voltage lower than the first power supply voltage. The positive feedback circuit accelerates transition speed when a compared result signal indicating a compared result between the input signal and the reference signal in voltage, is inverted, on the basis of the output signal of the differential input circuit. The imaging device further includes a voltage conversion circuit that converts the output signal of the differential input circuit into a signal corresponding to the second power supply voltage.

Abstract: Systems and methods are described for determining a phase measurement difference between a received modulated signal and a local clock signal. An adjusted local clock phase measurement may be determined by subtracting, from the phase measurement difference, a phase correction that is based on the frequency difference between the modulator signal's carrier frequency and the local clock's frequency. A phase modulation value may be generated by scaling the adjusted local clock phase measurement. The scaling may be based on a ratio of the modulated signal's carrier frequency and the local clock's frequency. The phase correction may be based on (i) a count of periods of the modulated signal occurring between each corrected phase measurement and (ii) a difference between the carrier frequency and the local clock frequency.

Abstract: A digital-to-analog converter circuit including one or more digital-to-analog converter cells and a separate voltage protection circuit connected by a common output node. A first digital-to-analog converter cell includes a first transistor which is configured to be switched to a conductive state when the first digital-to-analog converter cell is activated. A first terminal of the first transistor is coupled to a defined potential, wherein a second terminal of the first transistor is coupled to a common output node of the one or more digital-to-analog converter cells. The digital-to-analog converter circuit further includes a voltage protection circuit coupled between the common output node of the one or more digital-to-analog converter cells and an output node of the digital-to-analog converter circuit to regulate a voltage between the common output node and the defined potential.