Patents Examined by Jean B. Jeanglaude
  • Patent number: 10396814
    Abstract: A circuit, which is usable in a flash analog-to-digital converter, includes a first switch configured to provide a first reference voltage to a first reference node responsive to a first control signal and a second switch configured to provide the first reference voltage to a second reference node responsive to a second control signal. A third switch is coupled to the first switch and is configured to provide a second reference voltage to the first reference node responsive to a clock signal. Further, a fourth switch is coupled to the second switch and configured to provide the second reference voltage to the second reference node responsive to the clock signal.
    Type: Grant
    Filed: December 6, 2018
    Date of Patent: August 27, 2019
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jafar Sadique Kaviladath, Neeraj Shrivastava
  • Patent number: 10367520
    Abstract: A subtractor circuit can be fabricated within an integrated circuit (IC) and can be configured to draw a difference output node to a voltage proportional to a difference between two received N-bit binary numbers. The subtractor circuit includes sets of N inputs that receive N-bit binary numbers, each set of N inputs indexed by an integer bit number “n.” The subtractor circuit includes two sets of scaled capacitors, each capacitor of one set connected to an nth input of the corresponding set of N inputs and to the difference output node. Each scaled capacitor has a capacitance equal to 2(n)*a unit capacitance (CUNIT). The subtractor circuit includes a reference capacitor connected to ground and the difference output node, and a reset circuit configured to draw, in response to a received RESET signal, the difference output node to ground.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 30, 2019
    Assignee: International Business Machines Corporation
    Inventors: David Paulsen, Phil Paone, John E. Sheets, II, George Paulik, Karl Erickson, Gregory J. Uhlmann
  • Patent number: 10361472
    Abstract: A Cubesat uses both rail rods, walls, or both as an antenna. Either the rail rods and/or walls may form a rectangular waveguide, and may have one or more slots that allow energy to leak and radiate in a predefined direction in space.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: July 23, 2019
    Assignee: The United States of America as represented by the Administrator of NASA
    Inventor: Manohar Deshpande
  • Patent number: 10361485
    Abstract: In accordance with the concepts, systems, methods and techniques described herein a tripole current loop radiating element is provided having three conductors disposed on a substrate with the three conductors being physically spaced apart from each other and arranged to be responsive to radio frequency (RF) signals at a desired frequency range. Each of the three conductors includes a ground via to couple the respective conductor to a ground plane and a signal via to receive RF signals from a single feed circuit. The feed circuit includes a signal port, and first, second and third antenna ports, with each of the antenna ports coupled to a respective one of the three conductors. The feed circuit can provide the RF signals to each of the three conductors having equal amplitudes and distributed with relative phases of 0°/120°/240° respectively (i.e., phase shifted by 120° from an adjacent conductor).
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 23, 2019
    Assignee: Raytheon Company
    Inventor: Robert S. Isom
  • Patent number: 10361715
    Abstract: Provided are systems and methods, including an integrated circuit, for data decompression of data encoded using a fixed-length encoding technique. For a data set where some symbols appear more frequently than others, the frequent symbols can be encoded into a short encoded symbol, and the remaining symbols can be encoded into a long encoded symbol. A decompression circuit can include decoder circuits that, upon receiving a set of input bits, can determine whether the set of input bits include one long encoded symbol or one or more short encoded symbols. The decoder circuit can then decode the one long encoded symbol or the one or more short encoded symbol. The fixed length of the encoded symbols can enable the decompression circuit to output decoded symbols at a same rate at which the circuit receives encoded symbols.
    Type: Grant
    Filed: June 4, 2018
    Date of Patent: July 23, 2019
    Assignee: Amazon Technologies, Inc.
    Inventor: Raymond Scott Whiteside
  • Patent number: 10355706
    Abstract: A method and system for calibrating a time-interleaved digital to analog converter (DAC) provides equalization of frequency response misalignments in sub-DACs forming the DAC. In a calibration mode, test signals are applied to an DAC and output amplitudes and phases of are measured. From the measured values, complex values of the gains of the respective sub-DACs. hm(F) are determined and a specified target frequency response T(F) for a tandem connection equalizer-DAC is determined. For each of a plurality of test frequencies, complex values of equalizer gains Eqm are determined from Eqm(F)=T(F)/hm(F), to form equalizing frequency responses. Sets of equalizing coefficients Cm(p) pursuant to discrete Fourier transforms on Eqm(F). In an operation mode, a digital input signal is transformed input into an equalized digital signal E(n) through use of the sets of equalizing coefficients Cm(p).
    Type: Grant
    Filed: November 28, 2018
    Date of Patent: July 16, 2019
    Assignee: Guzik Technical Enterprises
    Inventors: Anatoli B. Stein, Semen P. Volfbeyn, Alexander Taratorin, Valeriy Serebryanskiy
  • Patent number: 10355708
    Abstract: An idle tone dispersion device outputs a frequency delta-sigma modulation signal obtained by using either one of a reference signal and a measured signal to perform frequency delta-sigma modulation of the other and dispersing an idle tone. The idle tone dispersion device includes n (n is any natural number equal to or larger than 2) frequency delta-sigma modulation sections and an adder configured to add up output signals of the n frequency delta-sigma modulation sections and output the frequency delta-sigma modulation signal. Each of the n frequency delta-sigma modulation sections uses either one of the reference signal and the measured signal to perform the frequency delta-sigma modulation of the other. At least one of the reference signal and the measured signal includes jitter including a frequency component higher than a frequency of an idle tone of an output signal of the frequency delta-sigma modulation section.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: July 16, 2019
    Assignee: Seiko Epson Corporation
    Inventor: Masayoshi Todorokihara
  • Patent number: 10355709
    Abstract: A sigma-delta ADC circuit with an analog loop filter circuit can be multiplexed between different inputs by flushing the memory of the analog loop filter integrators and the digital decimation filter and filling it with new data for the current input. However, filling the memory can be slow with respect to the sampling frequency because the information about past history has to be built up before meaningful output data can be generated. Thus, the multiplexing rate between channels using a sigma-delta ADC circuit can be slowed by such memory flushing. A multiplexed sigma-delta ADC circuit is described that can overcome these problems so as to be able to support cycle-by-cycle sampling of multiple channels. These techniques can provide a fast sigma-delta analog-to-digital converter (ADC) circuit that is small in area and that can multiplex over a number of channels dynamically.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: July 16, 2019
    Assignee: Analog Devices, Inc.
    Inventors: Yogesh Jayaraman Sharma, Arthur J. Kalb
  • Patent number: 10355370
    Abstract: A phased array has a laminar substrate, a plurality of elements on the laminar substrate forming a patch phased array, and first and second sets of integrated circuits on the laminar substrate. The first set of integrated circuits, each of which are single polarity integrated circuits, connects with a first set of the plurality of elements, and are configured to operate using first signals having a first polarity. In a similar manner, each one of the second set of integrated circuits also is a single polarity integrated circuit and connects with a second set of the plurality of elements. Also, each of the second set of integrated circuits is configured to operate using second signals having a second polarity. The first polarity is substantially orthogonal to the second polarity (i.e., to not interfere with each other).
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: July 16, 2019
    Assignee: ANOKIWAVE, INC.
    Inventors: Robert J. McMorrow, Robert Ian Gresham
  • Patent number: 10348319
    Abstract: Techniques to use reservoir capacitors in ADC to supply most of the charge to bit-trial capacitors as bit-trials are performed. An accurate reference voltage source, e.g., a reference buffer circuit, only needs to supply the difference, e.g., an inaccuracy, in the charge supplied by the reservoir capacitors. Instead of having to resettle for each bit-trial, the accurate reference voltage source has only to deliver the initial charge to the reservoir capacitors during acquisition and once more when the ADC is ready to sample onto the residue amplifier. These techniques can ease the demands on the reference buffer circuit and requirement of external decoupling capacitors, for example.
    Type: Grant
    Filed: May 18, 2018
    Date of Patent: July 9, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Sandeep Monangi, Anoop Manissery Kalathil, Vinayak Mukund Kulkarni, Michael C. W. Coln
  • Patent number: 10348072
    Abstract: A floor cable channel is provided for positioning a cable line element on an underlying surface and for protecting the cable line element. The floor cable channel includes a first channel element and a second channel element for receiving the cable line element and a connection element connecting the first channel element to the second channel element. The connection element allows a rotational movement of the first channel element relative to the second channel element. The floor cable channel can be brought into a transport position in which the channel elements are parallel to each other and into an operating position in which the channel elements are arranged along their longitudinal axes. In the operating position, the first and second channel elements are in contact at their mutually facing front faces to provide a self-locking of the channel elements relative to each other in the operating position.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: July 9, 2019
    Assignee: Race Result AG
    Inventors: Konstantin Gaiser, Nikias Klohr
  • Patent number: 10348322
    Abstract: A semiconductor device includes a trimming circuit for a power management circuit. The trimming circuit includes an analog to digital converter (ADC) circuit with a comparator circuit, a successive approximation register (SAR) circuit having an input coupled to an output of the comparator circuit, a control circuit coupled to the SAR circuit, a digital to analog converter (DAC) circuit having inputs selectively couplable to digital output signals of the SAR circuit and an output coupled to a first input of the comparator circuit, and a variable resistance circuit configured to be selectively coupled to output signals of the ADC circuit.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: July 9, 2019
    Assignee: NXP USA, Inc.
    Inventors: Jae Woong Jeong, Leroy Winemberg
  • Patent number: 10347966
    Abstract: An electronic device includes a housing antenna formed from a conductive material. At least parts of a side member and a rear cover that constitute the housing of the electronic device are used as an antenna. Accordingly, radiation patterns generated by this antenna are formed on the rear surface of the electronic device as well as at the upper portion of the electronic device. It is therefore possible to perform wireless communication with higher accuracy.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: July 9, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woosup Lee, Hyunjeong Lee, Bumjin Cho, Hongil Kwon, Gaeun Lee, Soyoung Lee, Changho Lee, Chihyun Cho, Jaebong Chun
  • Patent number: 10347993
    Abstract: An antenna module installation system comprising a baseplate and a carrier chassis. The baseplate is configured to couple to an antenna dish assembly, and comprises an antenna module mounting apparatus including an alignment portion and a retention portion. The carrier chassis is configured to retain an antenna module, such as antenna hub amplifier, and comprises an engaging apparatus. The carrier chassis is configured to allow multiple manufacturers versions of a component to be used through adapter components. The engaging apparatus is configured to engage with the alignment portion, which positions the carrier chassis in a mounting alignment, and to move from the alignment portion to the retention portion which retains the carrier chassis in engagement with the baseplate. The engaging apparatus is designed to allow that direct connections to the component in the carrier chassis are disconnected prior to its removal.
    Type: Grant
    Filed: August 30, 2017
    Date of Patent: July 9, 2019
    Assignee: HUGHES NETWORK SYSTEMS, LLC
    Inventors: Peter McLaren, Kumud Patel
  • Patent number: 10340595
    Abstract: A dipole antenna is provided, which may include a substrate, a first radiator and a second radiator disposed thereon. The substrate may include a first metal layer and a second metal layer; the first metal layer may include a feed point connected to the signal wire of a coaxial cable; the second metal layer may include a ground point connected to the ground layer of the coaxial cable. The first radiator may include a first planar connection part and a first solid radiating part; the first planar connection part may be disposed on one end of the first solid radiating part and connected to the first metal layer. The second radiator may include a second planar connection part and a second solid radiating part; the second planar connection part may be disposed on one end of the second solid radiating part and connected to the second metal layer.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: July 2, 2019
    Assignee: ARCADYAN TECHNOLOGY CORPORATION
    Inventors: Shin-Lung Kuo, Shih-Chieh Cheng
  • Patent number: 10338820
    Abstract: A system architecture conserves memory bandwidth by including compression utility to process data transfers from the cache into external memory. The cache decompresses transfers from external memory and transfers full format data to naive clients that lack decompression capability and directly transfers compressed data to savvy clients that include decompression capability. An improved compression algorithm includes software that computes the difference between the current data word and each of a number of prior data words. Software selects the prior data word with the smallest difference as the nearest match and encodes the bit width of the difference to this data word. Software then encodes the difference between the current stride and the closest previous stride. Software combines the stride, bit width, and difference to yield final encoded data word. Software may encode the stride of one data word as a value relative to the stride of a previous data word.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: July 2, 2019
    Assignee: NVIDIA CORPORATION
    Inventors: Rouslan Dimitrov, Jeff Pool, Praveen Krishnamurthy, Chris Amsinck, Karan Mehra, Scott Cutler
  • Patent number: 10333543
    Abstract: Techniques that allow application of noise-shaped dither without applying dither at sampling, resulting in the analog-to-digital converter (ADC) circuit advantageously being balanced during acquisition. Balancing the ADC circuit at acquisition can reduce the risk of sampling digital interferences that can couple in through the references or substrates.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: June 25, 2019
    Assignee: Analog Devices Global Unlimited Company
    Inventors: Christopher Peter Hurrell, Hongxing Li, Colin G. Lyden
  • Patent number: 10331558
    Abstract: Systems, apparatuses, and methods for efficiently moving data for storage and processing. A compression unit within a processor includes multiple hardware lanes, selects two or more input words to compress, and for assigns them to two or more of the multiple hardware lanes. As each assigned input word is processed, each word is compared to an entry of a plurality of entries of a table. If it is determined that each of the assigned input words indexes the same entry of the table, the hardware lane with the oldest input word generates a single read request for the table entry and the hardware lane with the youngest input word generates a single write request for updating the table entry upon completing compression. Each hardware lane generates a compressed packet based on its assigned input word.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: June 25, 2019
    Assignee: Apple Inc.
    Inventors: Ali Sazegari, Charles E. Tucker, Jeffry E. Gonion, Gerard R. Williams, III, Chris Cheng-Chieh Lee
  • Patent number: 10326418
    Abstract: A circuit includes an input transistor pair with first and second input transistors, the first input transistor having a control terminal configured to receive an input signal and a cascode transistor pair including a first and second cascode transistors having a common control node. A bias circuit has a bias input configured to receive the input signal and a first bias output coupled to the common node of the first and second cascode transistors. The bias circuit includes a signal tracking circuit operating to generate the first bias output to track the input signal. A pair of load transistors are coupled to the input transistor pair and biased by a second bias output of the bias circuit.
    Type: Grant
    Filed: May 17, 2018
    Date of Patent: June 18, 2019
    Assignee: STMicroelectronics S.r.l.
    Inventors: Stefano Ramorini, Alberto Cattani, Alessandro Gasparini, Germano Nicollini
  • Patent number: 10326462
    Abstract: Methods and systems for time interleaved analog-to-digital converter timing mismatch calibration and compensation may include receiving an analog signal on a chip, converting the analog signal to a digital signal utilizing a time interleaved analog-to-digital-converter (ADC), and reducing a blocker signal that is generated by timing offsets in the time interleaved ADC by estimating complex coupling coefficients between a desired digital output signal and the blocker signal utilizing a decorrelation algorithm on frequencies within a desired frequency bandwidth. The decorrelation algorithm may comprise a symmetric adaptive decorrelation algorithm. The received analog signal may be generated by a calibration tone generator on the chip. An aliased signal may be summed with an output signal from a multiplier. The complex coupling coefficients may be determined utilizing the decorrelation algorithm on the summed signals.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: June 18, 2019
    Assignee: Maxlinear, Inc.
    Inventors: Pawandeep Taluja, Mingrui Zhu, Xuefeng Chen, Anand Anandakumar, Sheng Ye, Timothy Gallagher