Patents Examined by Jeffery S Zweizig
  • Patent number: 11675380
    Abstract: A voltage regulator circuit may generate a regulated voltage level using a voltage level of a feedback node. The regulated voltage level may be distributed, via a power distribution network, to package power supply node of a package, into which an integrated circuit has been mounted. Power switches included in the integrated circuit may couple the package power supply node to respective local power supply nodes in the integrated circuit. A particular power switch may selectively couple different ones of the local power supply nodes to the feedback node, allowing the voltage regulator circuit to compensate for reductions in the regulated voltage level due to the power distribution network, as well as adjust the regulated voltage level based on power consumptions of load circuits coupled to the local power supply nodes.
    Type: Grant
    Filed: April 7, 2022
    Date of Patent: June 13, 2023
    Assignee: Apple Inc.
    Inventors: Shawn Searles, Victor Zyuban, Mohamed Abu-Rahma
  • Patent number: 11677317
    Abstract: A control device includes a control IC that receives power supply from a power source unit activated by a first signal, and that is configured to control driving of the power source unit, a first signal acquisition unit configured to acquire the first signal, a detection unit configured to detect rising and falling of the first signal, a second signal output unit configured to output a second signal when the falling of the first signal is detected by the detection unit, and a lowering unit configured to lower, according to the second signal output from the second signal output unit, a voltage value of a terminal of the power source unit, to which the first signal is to be input, to a predetermined value or less for a predetermined period of time set in advance.
    Type: Grant
    Filed: April 12, 2022
    Date of Patent: June 13, 2023
    Assignee: AISIN CORPORATION
    Inventors: Masaki Yokota, Motofumi Miyake, Hiroaki Takahashi
  • Patent number: 11669115
    Abstract: Systems and methods as described herein may take a variety of forms. In one example, systems and methods are provided for a circuit for powering a voltage regulator. A voltage regulator circuit has an output electrically coupled to a gate of an output driver transistor, the output driver transistor having a first terminal electrically coupled to a voltage source and a second terminal electrically coupled to a first terminal of a voltage divider, the voltage divider having an second terminal electrically coupled to ground, and the voltage divider having an output of a stepped down voltage. A power control circuitry transistor has a first terminal electrically coupled to the voltage source, the power control circuitry transistor having a second terminal electrically coupled to the gate terminal of the output driver transistor, and the power control circuitry transistor having a gate terminal electrically coupled to a status voltage signal.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: June 6, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Szu-Chun Tsao, Jaw-Juinn Horng, Bindu Madhavi Kasina, Yi-Wen Chen
  • Patent number: 11670487
    Abstract: Bias supplies and plasma processing systems are disclosed. One bias supply comprises an output node, a return node, and a switch network and at least one power supply coupled to the output node and the return node. The switch network and the at least one power supply configured, in combination, to apply an asymmetric periodic voltage waveform and provide a corresponding current waveform at the output node relative to the return node. A metrology component is configured to receive and sample voltage and current signals indicative of a full cycle of the periodic voltage waveform and the corresponding current waveform to provide digital representations of a full cycle of the asymmetric periodic voltage waveform and a full cycle of the corresponding current waveform.
    Type: Grant
    Filed: January 26, 2022
    Date of Patent: June 6, 2023
    Assignee: Advanced Energy Industries, Inc.
    Inventor: Hien Minh Nguyen
  • Patent number: 11658577
    Abstract: A semiconductor device includes a plurality of voltage regulators arranged in a field programmable array and a power array controller coupled to the plurality of voltage regulators. The power array controller is configured to control the plurality of voltage regulators to output power to a plurality of power rails. Each power rail provides a respective rail current at a respective rail voltage. The power array controller is configured to for each of the plurality of power rails, determine the respective rail current associated with the respective power rail, select a subset of voltage regulators according to at least the respective rail current, and enable the subset of voltage regulators to generate the respective rail voltage and provide the respective rail current collectively.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: May 23, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Peng Zou, Gang Ren, Syrus Ziai, Curtis Roger McAllister
  • Patent number: 11658560
    Abstract: In a system for feeding a DC link and a method for operating the system, a sensor for detecting a current in the DC link or voltage on the DC link is connected to a controller, which activates a second converter, e.g., a DC/DC converter or current controller. A first energy storage device is connected via the second converter to the DC link, and the controller activates a third converter, e.g., a DC/DC converter or current controller. A second energy storage device is connected via the third converter to the DC link, and the first and the second energy storage devices are different, e.g., have a different dynamic behavior and/or different discharge time constants.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: May 23, 2023
    Assignee: SEW-EURODRIVE GMBH & CO. KG
    Inventors: Patrick Schmich, Simon Zeller
  • Patent number: 11652404
    Abstract: A method for calibrating currents includes performing a first sorting operation on a plurality of first current sources according to current levels generated by the first current sources, performing a second sorting operation on a plurality of second current sources according to current levels generated by the second current sources, determining a first switching sequence for the first plurality of current sources according to a result of the first sorting operation, and determining a second switching sequence for the second plurality of current sources according to a result of the second sorting operation and the first switching sequence. The plurality of first current sources have a same target current value, and the plurality of second current sources have a same target current value.
    Type: Grant
    Filed: March 11, 2022
    Date of Patent: May 16, 2023
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Yi-Ching Liao, Chih-Yu Chen, Yu Hsun Hung, Juei Chin Shen
  • Patent number: 11646665
    Abstract: Circuits and methods for providing a “bootstrap” power supply for level-shifter/driver (LS/D) circuits in a FET-based power converter. In a first embodiment, linear regulators and a bootstrap capacitor provide a bootstrap power supply for level-shifter/driver circuits in each tier of a multi-level FET-based power converter. In a second embodiment, floating charge circuits and bootstrap capacitors provide an improved bootstrap power supply for level-shifter and driver circuits in each tier of a multi-level FET-based power converter. More particularly, a floating charge circuit configured to be coupled to an associated bootstrap capacitor includes a first sub-circuit configured to pre-charge the associated bootstrap capacitor when coupled and a second sub-circuit configured to transfer charge between the bootstrap capacitor and a bootstrap capacitor coupled to an adjacent floating charge circuit.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: May 9, 2023
    Assignee: pSemi Corporation
    Inventor: Gary Chunshien Wu
  • Patent number: 11646658
    Abstract: Charge pump stages are coupled between flying capacitor pairs and arranged in a cascaded between a bottom voltage line and an output voltage line. Gain stages apply pump phase signals having a certain amplitude to the charge pump stages via the flying capacitors. A feedback signal path from the output voltage line to the bottom voltage line applies a feedback control signal to the bottom voltage line. Power supply for the gain stages is provided by a voltage of the feedback control signal in order to control the amplitude of the pump phase signals. An asynchronous logic circuit generates the switching drive signals for the gain stages with a certain switching frequency which is a function of a logic supply voltage derived from the voltage of the feedback control signal.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: May 9, 2023
    Assignee: STMicroelectronics S.r.l.
    Inventors: Stefano Ramorini, Alessandro Gasparini, Alberto Cattani
  • Patent number: 11641159
    Abstract: Circuits and methods that can rapidly detect voltage degradation in a positive charge pump output and discharge control node accumulated charge (CNAC), thereby forcing the positive charge pump into a high-power mode. Embodiments include circuitry configured to provide a load current to a positive charge pump, including a low-dropout regulator (LDO) having a pass device that includes a control input, and a rapid charge transfer circuit coupled to the control input of the pass device and configured to be coupled to a source of a trigger voltage, the rapid charge transfer circuit configured to transfer a charge to or from the control input of the pass device when the trigger voltage falls sufficiently below a specified level so as to rapidly place the pass device in a higher conduction state, and to automatically cease to provide the transfer the charge after a settable amount of time.
    Type: Grant
    Filed: November 16, 2021
    Date of Patent: May 2, 2023
    Assignee: pSemi Corporation
    Inventor: Robert Mark Englekirk
  • Patent number: 11641160
    Abstract: A power providing circuit and a power providing method are provided. The power providing circuit includes at least one first charge pump circuit, at least one second charge pump circuit, a first control circuit, a signal latch, and a voltage detector. The first charge pump circuit is configured to receive a first clock to generate a first pump voltage. The second charge pump circuit is configured to receive the first clock to generate the first pump voltage. The first control circuit is configured to provide the first clock to the first charge pump circuit and the at second charge pump circuit according to a power-on detection signal. The signal latch is coupled to the second charge pump circuit. The voltage detector is configured to receive an operation voltage and generate the power-on detection signal by detecting the operation voltage.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: May 2, 2023
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Chih-Jen Chen
  • Patent number: 11637356
    Abstract: In certain aspects, a receiving circuit includes a splitter, a first receiver, a second receiver, and a boost circuit. The splitter is configured to receive an input signal, split the input signal into a first signal and a second signal, output the first signal to the first receiver, and output the second signal to the second receiver. In certain aspects, the voltage swing of the input signal is split between the first signal and the second signal. The boost circuit may be configured to shift a supply voltage of the second receiver to boost a gate-overdrive voltage of a transistor in the second receiver during a transition of the input signal (e.g., transition from low to high). In certain aspects, the boost circuit controls the gate-overdrive voltage boosting based on the first signal and the second signal.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: April 25, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Aliasgar Presswala, Wilson Jianbo Chen, Chiew-Guan Tan
  • Patent number: 11619961
    Abstract: A bandgap reference correction circuit comprising a bandgap reference circuit comprising a first resistor; a first oscillator comprising a second resistor, wherein a frequency of a first oscillator output signal of the first oscillator depends on a resistance of the second resistor; and a compensation module configured to: receive the first oscillator output signal from the first oscillator and a reference frequency signal from a reference oscillator; determine the frequency of the first oscillator output signal using the reference frequency signal; and set a resistance of the first resistor based on the frequency of the first oscillator output signal.
    Type: Grant
    Filed: December 23, 2021
    Date of Patent: April 4, 2023
    Assignee: NXP USA, Inc.
    Inventors: Stefano Pietri, John Pigott
  • Patent number: 11621634
    Abstract: An electronic device includes a hysteresis circuit, a voltage divider circuit, a control circuit, and a discharge resistor. The hysteresis circuit has a first threshold voltage and a second threshold voltage. The hysteresis circuit generates a hysteresis voltage according to an output voltage at an output node. The voltage divider circuit generates a divided voltage according to the output voltage and the hysteresis voltage. The control circuit has a reference voltage and monitors the divided voltage. If the divided voltage is lower than the reference voltage, the control circuit will use the discharge resistor to perform a discharging operation to the output voltage at the output node.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: April 4, 2023
    Assignee: QUANTA COMPUTER INC.
    Inventor: Hsin-Chih Kuo
  • Patent number: 11614763
    Abstract: An aspect of the disclosure relates to a reference voltage generator, including: a first field effect transistor (FET) including a first threshold voltage; a second FET including a second threshold voltage different than the first threshold voltage; a gate voltage generator coupled to gates of the first and second FETs; a first current source coupled in series with the first FET between first and second voltage rails; a second current source; and a first resistor coupled in series with the second current source and the second FET between the first and second voltage rails, wherein a reference voltage is generated across the first resistor.
    Type: Grant
    Filed: January 4, 2022
    Date of Patent: March 28, 2023
    Assignee: QUALCOMM INCORPORATED
    Inventors: Debesh Bhatta, Sulin Li, Shitong Zhao, Hui Wang, John Abcarius
  • Patent number: 11609279
    Abstract: Vehicles and related systems and methods are provided for monitoring health of a power conversion module. A method involves operating the power conversion module to conduct a heating current until reaching a steady-state temperature, obtaining measurement data for an electrical characteristic associated with the power conversion module after reaching the steady-state temperature, determining a current thermal characterization curve for the power conversion module based on the measurement data and comparing the current thermal characterization curve to one or more reference thermal characterization curves for the power conversion module to identify a deviation associated with the current thermal characterization curve.
    Type: Grant
    Filed: March 9, 2022
    Date of Patent: March 21, 2023
    Assignee: GM GLOBAL TECHNOLOGY OPERATIONS LLC
    Inventor: Jinming Xu
  • Patent number: 11604490
    Abstract: Techniques and apparatus for reducing low frequency power supply spurs in clock signals. One example circuit generally includes a first power supply circuit configured to generate a first power supply voltage on a first power supply rail, a second power supply circuit configured to generate a second power supply voltage on a second power supply rail, a clock distribution network, and a feedback circuit coupled between the second power supply rail and at least one input of the first power supply circuit. The feedback circuit may be configured to sense the second power supply voltage, to process the sensed second power supply voltage, and to output at least one feedback signal to control the first power supply circuit based on the processed second power supply voltage. The clock distribution network may include first and second sets of clock drivers powered by the first and second power supply voltages, respectively.
    Type: Grant
    Filed: October 13, 2021
    Date of Patent: March 14, 2023
    Assignee: XILINX, INC.
    Inventors: Roswald Francis, Edward Cullen
  • Patent number: 11601123
    Abstract: Embodiments of power-on reset (POR) circuits are described. In one embodiment, a POR circuit includes a primary ladder circuit connected to a supply voltage and configured to generate a reference signal for a reset signal in response to the supply voltage and a secondary ladder circuit connected to the supply voltage and configured to bias the primary ladder circuit in response to the supply voltage.
    Type: Grant
    Filed: November 10, 2021
    Date of Patent: March 7, 2023
    Assignee: NXP B.V.
    Inventors: Shubham Ajaykumar Khandelwal, Henricus Cornelis Johannes Büthker, Hendrik Johannes Bergveld
  • Patent number: 11594958
    Abstract: Driver circuitry for driving a load based on an input signal, comprising: at least one variable boost stage comprising: first and second input nodes configured to receive a first voltage and a second voltage respectively; first and second flying capacitor nodes for connection to a flying capacitor therebetween; a network of switching paths for selectively connecting the first and second input nodes with the first and second flying capacitor nodes; an output stage for selectively connecting a driver output node to each of the first and second flying capacitor nodes; and a controller operable in a first boost mode to: control the output stage to selectively connect the driver output node to the first flying capacitor node; control the network of switching paths to switch connection of the second flying capacitor node between the first and second input nodes at a controlled duty cycle; and in a first charge top-up cycle, control the network of switching paths to connect the first input node to the first flying c
    Type: Grant
    Filed: November 30, 2021
    Date of Patent: February 28, 2023
    Assignee: Cirrus Logic, Inc.
    Inventors: Eric J. King, Axel Thomsen, Anthony S. Doy, Thomas H. Hoff, John L. Melanson
  • Patent number: 11594961
    Abstract: An apparatus includes a controller. The controller monitors a magnitude of first current supplied by an output voltage of a first power converter to power a dynamic load. The controller controls a second power converter to supply second current through the dynamic load based on the monitored magnitude of first current.
    Type: Grant
    Filed: July 19, 2021
    Date of Patent: February 28, 2023
    Assignees: Infineon Technologies Austria AG, Cypress Semiconductor (Canada), Inc.
    Inventors: Darryl Tschirhart, Danny Clavette