Patents Examined by Jenny L Wagner
  • Patent number: 10575405
    Abstract: A module includes a wiring board, an insulating layer that is laminated on the bottom surface of the wiring board, a ring-shaped coil core that is embedded in the insulating layer, a coil electrode that is wound around the coil core, electronic components that are disposed in an inner region surrounded by the coil core in the insulating layer, and an electronic component that is mounted on or in the top surface of the wiring board. With this configuration, the areas of main surfaces of the wiring board and main surfaces of the insulating layer are not large, whereas if the electronic components were mounted on or in the top surface of the wiring board, the areas of the main surfaces of the wiring board and the main surfaces of the insulating layer would be large, and a reduction in the size of the module can be facilitated.
    Type: Grant
    Filed: August 4, 2017
    Date of Patent: February 25, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventor: Toshiro Adachi
  • Patent number: 10571956
    Abstract: The present disclosure provides a display panel and a display device. The display panel includes a first substrate, a second substrate, and at least one support structure. The first substrate and the second substrate are disposed opposite to each other. A region between the first substrate and the second substrate includes a display region and an encapsulation region surrounding the display region. A distance between the first substrate and the second substrate corresponding to the display region is h1, and a distance between the first substrate and the second substrate corresponding to the encapsulation region is h2, where h1>h2. The at least one support structure is disposed between the display region and the encapsulation region, and each of the at least one support structure has a height of h3, where h2<h3<h1.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: February 25, 2020
    Assignee: WUHAN TIANMA MICRO-ELECTRONICS CO., LTD.
    Inventors: Yanhua Liu, Mingyan Huang
  • Patent number: 10575431
    Abstract: A supporting and positioning structure of server chassis including a metal plate combined with the chassis. A supporting body is combined at a lateral side of the mounting plate facing the server rack and includes a base and a pair of supporting plates. The base is fixed on the mounting plate, and the pair of supporting plates are arranged in parallel and at an interval so that a slot is formed therebetween. Moreover, a roller is rotatably disposed in the slot so that the chassis of the server rack can be supported and held.
    Type: Grant
    Filed: September 14, 2018
    Date of Patent: February 25, 2020
    Assignee: SUPER MICRO COMPUTER INC
    Inventors: Chanchi Yang, Chaoching Wu
  • Patent number: 10483041
    Abstract: A first outer electrode and first inner electrodes are supplied with an anode potential and a second outer electrode and second inner electrodes are supplied with a cathode potential when a monolithic ceramic capacitor is mounted and in use. The first outer electrode supplied with the anode potential has a thickness that is greater than a thickness of the second outer electrode supplied with the cathode potential.
    Type: Grant
    Filed: March 25, 2015
    Date of Patent: November 19, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Yoshito Saito, Satoshi Matsuno, Shinji Otani, Tomochika Miyazaki, Yasuhiro Nishisaka
  • Patent number: 10388460
    Abstract: A capacitor comprising first and second end sprays respectively located at distal ends of a capacitor cell, a positive polarity bus bar extending from a first wound conductive layer of the capacitor cell adjacent to the first end spray, a negative polarity bus bar extending from a second wound conductive layer of the capacitor cell adjacent to the second end spray, and a capacitor film wrapped around an area between the first and second conductive layers.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 20, 2019
    Assignee: Ford Global Technologies, LLC
    Inventors: Guangyin Lei, Xi Lu, Zhuxian Xu, Chingchi Chen
  • Patent number: 10370909
    Abstract: In accordance with embodiments of the present disclosure, a slickline for use in well drilling and hydrocarbon recovery operations includes a cable and an intermediate layer disposed around the cable. The slickline also includes a doped polymeric coating layered around the intermediate layer. The doped polymeric coating is a different material from the intermediate layer, and the doped polymeric coating includes a polymeric material doped with an element that is detectable within the doped polymeric coating via a detection machine for purposes of determining wear or other aspects about the conditions of the slickline.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: August 6, 2019
    Assignee: Halliburton Energy Services, Inc.
    Inventors: Sean Gregory Thomas, Wei Zhang, David L. Perkins
  • Patent number: 10103531
    Abstract: A component management system that can be customized by a user is provided. In some embodiments, the component management system includes a cover having first, second and third sides and a substantially uniform thickness, and a mounting panel having first and second major faces and first and second channels extending along opposite edges of the first and second major faces.
    Type: Grant
    Filed: June 15, 2016
    Date of Patent: October 16, 2018
    Assignee: Vpulse Inc.
    Inventor: William Ruhnke
  • Patent number: 9991053
    Abstract: A power capacitor, in particular a DC link capacitor, having a capacitor housing which has a first housing wall, in particular made of metal, which is galvanically connectable to a housing of an electronics unit, in particular a power electronics unit, and planar energizing units for energizing the power capacitor. A first subregion of a first energizing unit extends in an inner space of the housing adjacent to and at a distance from the first housing wall or from a different housing wall of the capacitor housing that is conductively connected to the first housing wall. A layer made of a dielectric material other than air is situated between the first subregion of the first energizing unit and this housing wall.
    Type: Grant
    Filed: November 5, 2010
    Date of Patent: June 5, 2018
    Assignee: ROBERT BOSCH GMBH
    Inventor: Hartmut Sparka
  • Patent number: 9961773
    Abstract: A printed circuit board assembly includes: a first signal terminal row including a plurality of first signal terminals connected to a plurality of signal wirings of a flexible printed circuit board (FPCB), respectively; a first ground terminal row spaced from the first signal terminal row and including a plurality of first ground terminals connected to a plurality of ground wirings of the FPCB, respectively; a second signal terminal row including a plurality of second signal terminals connected to a plurality of signal wirings of a printed circuit board (PCB), respectively; and a second ground terminal row spaced from the second signal terminal row and including a plurality of second ground terminals connected to a plurality of ground wirings of the PCB, respectively. The first ground terminal row is closer to an end portion of the FPCB than the first signal terminal row.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: May 1, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventor: Dongwan Choi
  • Patent number: 9947477
    Abstract: In a method of manufacturing a thin-film polymer multi-layer capacitor, in a vacuum chamber, a resin thin film layer forming step of forming a resin thin film layer by forming a monomer layer by vapor-depositing a monomer and thereafter by curing the monomer layer by irradiating an electron beam onto the monomer layer, and a metal thin film layer forming step of forming a metal thin film layer by vapor-depositing a metal material are alternately performed on a rotary drum thus forming a multi-layer body in which the resin thin film layer and the metal thin film layer are alternately laminated on the rotary drum. In the resin thin film layer forming step, the monomer layer is formed using a dimethacrylate compound having an alicyclic hydrocarbon skeleton expressed by a following chemical formula (1) as the monomer. wherein, symbol A indicates an organic group containing alicyclic hydrocarbon.
    Type: Grant
    Filed: February 10, 2014
    Date of Patent: April 17, 2018
    Assignee: RUBYCON CORPORATION
    Inventors: Shigeya Tomimoto, Tomonao Kako
  • Patent number: 9941522
    Abstract: A supercapacitor to be submerged in a medium containing a biological material and an oxidant, wherein the anode comprises a first enzyme that can catalyse the oxidation of the biological material and the cathode comprises a second enzyme that can catalyse the reduction of the oxidant, and wherein each of the anode and cathode electrodes consists of a solid agglomerate of a conductive material mixed with the first or the second enzyme, said agglomerate having a specific surface that is larger than or equal to 20 m2/g and an average pore size varying between 0.7 nm and 10 pm.
    Type: Grant
    Filed: March 4, 2014
    Date of Patent: April 10, 2018
    Assignee: Universite Joseph Fourier
    Inventors: Serge Cosnier, Michael Holzinger, Alan Le Goff, Charles Agnes
  • Patent number: 9941052
    Abstract: A multilayer ceramic capacitor includes a body and at least two outer electrodes. The body includes first and second main surfaces, an inner layer portion and first and second outer layer portions. In the inner layer portion, dielectric layers and conductive layers are alternately stacked on each other. The second outer layer portion includes an outer portion and an inner portion. A boundary region adjacent to the inner portion in the outer portion inclines toward the first main surface.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: April 10, 2018
    Assignee: Murata Manufacturing Co., Ltd.
    Inventors: Hiroaki Sugita, Shota Kitano
  • Patent number: 9936582
    Abstract: Embodiments of integrated circuit (IC) assemblies and related techniques are disclosed herein. For example, in some embodiments, an IC assembly may include a first printed circuit board (PCB) having a first face and an opposing second face; a die electrically coupled to the first face of the first PCB; a second PCB having a first face and an opposing second face, wherein the second face of the second PCB is coupled to the first face of the first PCB via one or more solder joints; and a molding compound. The molding compound may be in contact with the first face of the first PCB and the second face of the second PCB. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: April 30, 2014
    Date of Patent: April 3, 2018
    Assignee: INTEL CORPORATION
    Inventors: Junfeng Zhao, Saeed S. Shojaie, Cheng Yang
  • Patent number: 9934909
    Abstract: In an embodiment, a multilayer ceramic capacitor 10 has the first external electrode 12 and second external electrode 13 provided with a space between them on the other height-direction surface f6 of the capacitor body 11 in the length direction, where the width Wa of the other height-direction surface f6 of the capacitor body 11 is smaller than the width W of the one height-direction surface f5. The multilayer ceramic capacitor can improve yield and help reduce cost by allowing several of the conditions to be found non-defective in the appearance inspection.
    Type: Grant
    Filed: November 7, 2016
    Date of Patent: April 3, 2018
    Assignee: TAIYO YUDEN CO., LTD.
    Inventor: Yusuke Kowase
  • Patent number: 9928962
    Abstract: A multilayer ceramic capacitor includes a body and at least two outer electrodes. The body includes first and second main surfaces, an inner layer portion and first and second outer layer portions. In the inner layer portion, dielectric layers and conductive layers are alternately stacked on each other. The second outer layer portion includes an outer portion and an inner portion. A boundary region adjacent to the inner portion in the outer portion inclines toward the first main surface.
    Type: Grant
    Filed: September 28, 2017
    Date of Patent: March 27, 2018
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Hiroaki Sugita, Shota Kitano
  • Patent number: 9900989
    Abstract: The object of the present invention is to provide a printed circuit board formed with a cavity to mount a semiconductor chip.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: February 20, 2018
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Yong Jik Lee, Jung Kyung Sung, Bong Wan Koo, Hyun Duck Lim
  • Patent number: 9894752
    Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.
    Type: Grant
    Filed: April 3, 2015
    Date of Patent: February 13, 2018
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Gong Ouyang, Kai Xiao, Kemal Aygun, Beom-Taek Lee
  • Patent number: 9893003
    Abstract: This disclosure provides a package substrate, a flip-chip package circuit, and their fabrication methods. The package substrate includes: a first wiring layer having a first dielectric material layer and a first metal wire protruding from the first dielectric material layer; a conductive pillar layer formed on the first wiring layer and including a molding compound layer, a second dielectric material layer formed on the molding compound layer, and a metal pillar connected to the first metal wire; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer.
    Type: Grant
    Filed: October 22, 2014
    Date of Patent: February 13, 2018
    Assignee: PHOENIX PIONEER TECHNOLOGY CO., LTD.
    Inventors: Che-Wei Hsu, Shih-Ping Hsu
  • Patent number: 9872378
    Abstract: There are provided an electronic element mounting board and an electronic device capable of suppressing transmission of incident light to an electronic device through a circumferential edge part of an opening of a board and thus of reducing a noise level in receiving an image. An electronic element mounting board includes an insulating substrate. The insulating substrate has an opening and a lower surface, and an electronic element is disposed on the lower surface so as to overlap the opening in a plan view. A circumferential edge part of the opening of the insulating substrate has a porosity lower than a porosity of a portion outside the circumferential edge part. Since it is possible to suppress transmission of incident light to the electronic element through the circumferential edge part, it is possible to reduce a noise level in receiving an image in the electronic element.
    Type: Grant
    Filed: April 28, 2014
    Date of Patent: January 16, 2018
    Assignee: KYOCERA CORPORATION
    Inventors: Shuya Kubo, Kouki Suda, Tsuyoshi Ishimabushi, Shinji Ichiki, Yousuke Moriyama
  • Patent number: 9865480
    Abstract: The present invention relates to an under-fill dam with high detection probability that is composed of a dry film solder resist and provided in the form of a fence around a chip device in order to prevent leaks of an under-fill material filled in a gap between a substrate and the chip device.
    Type: Grant
    Filed: May 11, 2011
    Date of Patent: January 9, 2018
    Assignee: LG CHEM, LTD.
    Inventors: Byung-Ju Choi, Woo-Jae Jeong, Bo-Yun Choi, Kwang-Joo Lee, Min-Su Jeong