Abstract: A printed circuit board assembly includes: a first signal terminal row including a plurality of first signal terminals connected to a plurality of signal wirings of a flexible printed circuit board (FPCB), respectively; a first ground terminal row spaced from the first signal terminal row and including a plurality of first ground terminals connected to a plurality of ground wirings of the FPCB, respectively; a second signal terminal row including a plurality of second signal terminals connected to a plurality of signal wirings of a printed circuit board (PCB), respectively; and a second ground terminal row spaced from the second signal terminal row and including a plurality of second ground terminals connected to a plurality of ground wirings of the PCB, respectively. The first ground terminal row is closer to an end portion of the FPCB than the first signal terminal row.

Abstract: In a method of manufacturing a thin-film polymer multi-layer capacitor, in a vacuum chamber, a resin thin film layer forming step of forming a resin thin film layer by forming a monomer layer by vapor-depositing a monomer and thereafter by curing the monomer layer by irradiating an electron beam onto the monomer layer, and a metal thin film layer forming step of forming a metal thin film layer by vapor-depositing a metal material are alternately performed on a rotary drum thus forming a multi-layer body in which the resin thin film layer and the metal thin film layer are alternately laminated on the rotary drum. In the resin thin film layer forming step, the monomer layer is formed using a dimethacrylate compound having an alicyclic hydrocarbon skeleton expressed by a following chemical formula (1) as the monomer. wherein, symbol A indicates an organic group containing alicyclic hydrocarbon.

Abstract: A multilayer ceramic capacitor includes a body and at least two outer electrodes. The body includes first and second main surfaces, an inner layer portion and first and second outer layer portions. In the inner layer portion, dielectric layers and conductive layers are alternately stacked on each other. The second outer layer portion includes an outer portion and an inner portion. A boundary region adjacent to the inner portion in the outer portion inclines toward the first main surface.

Abstract: A supercapacitor to be submerged in a medium containing a biological material and an oxidant, wherein the anode comprises a first enzyme that can catalyse the oxidation of the biological material and the cathode comprises a second enzyme that can catalyse the reduction of the oxidant, and wherein each of the anode and cathode electrodes consists of a solid agglomerate of a conductive material mixed with the first or the second enzyme, said agglomerate having a specific surface that is larger than or equal to 20 m2/g and an average pore size varying between 0.7 nm and 10 pm.

Abstract: Embodiments of integrated circuit (IC) assemblies and related techniques are disclosed herein. For example, in some embodiments, an IC assembly may include a first printed circuit board (PCB) having a first face and an opposing second face; a die electrically coupled to the first face of the first PCB; a second PCB having a first face and an opposing second face, wherein the second face of the second PCB is coupled to the first face of the first PCB via one or more solder joints; and a molding compound. The molding compound may be in contact with the first face of the first PCB and the second face of the second PCB. Other embodiments may be disclosed and/or claimed.

Abstract: In an embodiment, a multilayer ceramic capacitor 10 has the first external electrode 12 and second external electrode 13 provided with a space between them on the other height-direction surface f6 of the capacitor body 11 in the length direction, where the width Wa of the other height-direction surface f6 of the capacitor body 11 is smaller than the width W of the one height-direction surface f5. The multilayer ceramic capacitor can improve yield and help reduce cost by allowing several of the conditions to be found non-defective in the appearance inspection.

Abstract: A multilayer ceramic capacitor includes a body and at least two outer electrodes. The body includes first and second main surfaces, an inner layer portion and first and second outer layer portions. In the inner layer portion, dielectric layers and conductive layers are alternately stacked on each other. The second outer layer portion includes an outer portion and an inner portion. A boundary region adjacent to the inner portion in the outer portion inclines toward the first main surface.

Abstract: The object of the present invention is to provide a printed circuit board formed with a cavity to mount a semiconductor chip.

Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.

Abstract: This disclosure provides a package substrate, a flip-chip package circuit, and their fabrication methods. The package substrate includes: a first wiring layer having a first dielectric material layer and a first metal wire protruding from the first dielectric material layer; a conductive pillar layer formed on the first wiring layer and including a molding compound layer, a second dielectric material layer formed on the molding compound layer, and a metal pillar connected to the first metal wire; a second wiring layer formed on the conductive pillar layer and including a second metal wire connected to the metal pillar; and a protection layer formed on the second wiring layer.

Abstract: There are provided an electronic element mounting board and an electronic device capable of suppressing transmission of incident light to an electronic device through a circumferential edge part of an opening of a board and thus of reducing a noise level in receiving an image. An electronic element mounting board includes an insulating substrate. The insulating substrate has an opening and a lower surface, and an electronic element is disposed on the lower surface so as to overlap the opening in a plan view. A circumferential edge part of the opening of the insulating substrate has a porosity lower than a porosity of a portion outside the circumferential edge part. Since it is possible to suppress transmission of incident light to the electronic element through the circumferential edge part, it is possible to reduce a noise level in receiving an image in the electronic element.

Abstract: A first printed circuit board (PCB) assembly can include an embedded electrical connector configured to be mechanically coupled to a corresponding tab-shaped portion of a second PCB assembly, such as to permit insertion of the tab-shaped portion of the second PCB assembly into the embedded electrical connector when the second PCB assembly is aligned in a specified orientation. In an example, the second PCB assembly can include an approximately planar conductive antenna.

Abstract: The present invention relates to an under-fill dam with high detection probability that is composed of a dry film solder resist and provided in the form of a fence around a chip device in order to prevent leaks of an under-fill material filled in a gap between a substrate and the chip device.

Abstract: A component-embedded substrate includes: a resin substrate having a mount surface and a peripheral surface surrounding a perimeter of the mount surface; a first mounted component mounted on the mount surface; a second mounted component mounted on the mount surface and spaced from the first mounted component; and a first embedded chip-type electronic component disposed in the resin substrate. The first embedded chip-type electronic component is located close to the peripheral surface of the resin substrate. The mount surface includes: a first region located between the first and second mounted components and extending along a cross direction crossing an arrangement direction along which the first and second mounted components are arranged with respect to each other; and a second region located outside the first region. The first embedded chip-type electronic component is arranged to extend in the first and second regions as seen from above the mount surface.

Abstract: An example method for attaching a ball grid array chip to a circuit board includes providing an adapter for attaching a chip with a plurality of solder balls to a circuit board, the adapter having an adapter substrate made from a material having substantially the same coefficient of thermal expansion as the substrate used in the chip and having at least one electrical contact site on a mounting surface of the adapter substrate for engaging a solder ball on the ball grid array chip and a plurality of lead wires extending from each side of the adapter substrate. At least one of the lead wires is electrically connected to at least one electrical contact site on the adapter substrate.

Abstract: The invention relates to a cased electrical component comprising a carrier substrate (10), a spring device (20), which is arranged on the carrier substrate (10), a chip (30), which on a first side (31) of the chip is coupled to the spring device (20), and a cover element (100), which is arranged on the carrier substrate (10). The cover element (100) is arranged over the chip (20) such that the cover element (100) is in contact with the chip (30) at least on a second side (32) of the chip, which is different from the first side. The component has a low space requirement and is highly sealed with respect to influences from the surroundings.

Abstract: In a component-embedded substrate, a component and wiring block units are embedded in a component-embedded layer; conductive layers are located on all surfaces of the wiring block units; the component and the wiring block units are arranged such that lower surface side conductive layers of the wiring block units and electrodes of the component contact lower surface side wiring layers; via-hole conductors are located in respective upper positions relative to upper surface side conductive layers of the wiring block units and the electrodes of the component; and upper surface side wiring layers of the component-embedded layer are thus electrically connected to upper surface side conductive layers of the wiring block units, and the electrodes of the component by the via-hole conductors.

Abstract: Some novel features pertain to a capacitor structure that includes a first conductive layer, a second conductive layer and a non-conductive layer. The first conductive layer has a first overlapping portion and a second overlapping portion. The second conductive layer has a third overlapping portion, a fourth overlapping portion, and a non-overlapping portion. The third overlapping portion overlaps with the first overlapping portion of the first conductive layer. The fourth overlapping portion overlaps with the second overlapping portion of the first conductive layer. The non-overlapping portion is free of any overlap (e.g., vertical overlap) with the first conductive layer. The non-conductive layer separates the first and second conductive layers. The non-conductive layer electrically insulates the third overlapping portion and the fourth overlapping portion from the first conductive layer.

Abstract: An all-flat sensor includes a coupling substrate; a sensing chip, which is disposed on the coupling substrate, has first electrodes arranged in an array and a first dielectric layer covering over the first electrodes, and is electrically connected to the coupling substrate; and a second dielectric layer covering over the sensing chip and providing an outlook color. An electronic device using the all-flat sensor is also provided.

Abstract: An electrical connection between two electrical harnesses is provided. The electrical harnesses include flexible printed circuits with embedded conductive tracks, each of which terminates in a receiving hole in a respective terminating region The terminating regions are connected together using conductive pins. The connection formation is then encapsulated by an encapsulating body formed of an insulating. The encapsulating body seals and protects the electrical connection, which is thus reliable and robust.