Patents Examined by Jeremy C. Norris
  • Patent number: 11330707
    Abstract: A carrier substrate (1) that includes an insulation layer (11) and a metal layer (12), wherein a flank profile (2), in particular an etching flank profile, at least zonally borders the metal layer (12) in a primary direction (P) extending parallel to the main extension plane (HSE), wherein, viewed in the primary direction (P), the flank profile (2) extends from a first edge (15) on an upper side (31) of the metal layer (12), which faces away from the insulation layer (11), to a second edge (16) on a lower side (32) of the metal layer (12), which faces the insulation layer (11), characterized in that the flank profile (2), viewed in the primary direction (P), has at least one local maximum (21) and at least one local minimum (22).
    Type: Grant
    Filed: September 24, 2019
    Date of Patent: May 10, 2022
    Assignee: ROGERS GERMANY GMBH
    Inventors: Stefan Britting, Xinhe Tang, Andreas Meyer, Andrea Adler
  • Patent number: 11330710
    Abstract: A metal-clad laminated board includes an insulating layer and a metal layer, in which the insulating layer includes a cured product of a resin composition containing a modified polyphenylene ether compound terminally modified with a substituent having an unsaturated double bond; and a crosslinkable curing agent having an unsaturated double bond in the molecule, and containing 40 to 250 parts by mass of silica particles with respect to 100 parts by mass in total of the modified polyphenylene ether compound and the crosslinkable curing agent, the resin composition contains 0.2 to 5 parts by mass of a first silane coupling agent having an unsaturated double bond in the molecule with respect to 100 parts by mass of the silica particles, and a contact surface of the metal layer in contact with the insulating layer is surface-treated with a second silane coupling agent having an amino group in the molecule.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: May 10, 2022
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Tatsuya Arisawa, Hirohisa Goto, Tomoyuki Abe
  • Patent number: 11330703
    Abstract: A wireless communication system includes a first differential signal line, a differential coupler, and an electronic circuit. The differential coupler has a second differential signal line to perform wireless communication of a differential signal with the first differential signal line via electromagnetic field coupling. The electronic circuit is connected to the differential coupler via a wired transmission path to process the differential signal. A surface of a board or a ground pattern of the electronic circuit is inclined or upright with respect to the second differential signal line so as to separate away from a direction in which the first differential signal line extends.
    Type: Grant
    Filed: October 16, 2020
    Date of Patent: May 10, 2022
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Hiroto Tamaki
  • Patent number: 11330699
    Abstract: Embodiments described herein are directed to methods and apparatus for power distribution. The apparatus can include a power distribution network for a plurality of integrated circuits (IC). According to embodiments, the power distribution network includes a plurality of overlapping power/ground (PG) plane segments and one or more non-overlapping PG (no-PG) plane segments. Each overlapping-PG plane segment is separated from another overlapping-PG plane segment by at least one no-PG plane segment. The no-PG plane segments can include at least one of a multilayered power (P) plane segment with no ground reference of any PG plane and a multilayered ground (G) plane segment with no power reference of any PG plane.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: May 10, 2022
    Assignees: San Diego State University Research Foundation, Kyocera International, Inc., Fraunhofer-Gesellschaft zur Foerderung der angewandten Forschung e.V.
    Inventors: Arif Ege Engin, Gerardo Aguirre, Klaus-Dieter Lang, Ivan Ndip
  • Patent number: 11330711
    Abstract: The present invention is directed to flexible conductive articles (600) that include a printed circuit (650) and a stretchable or non-stretchable substrate (610). In some embodiments, the substrate has a printed circuit on both sides. The printed circuit contains N therein a porous synthetic polymer membrane (660) and an electrically conductive trace (670) as well as a non-conducive region (640). The electrically conductive trace is imbibed or otherwise incorporated into the porous synthetic polymer membrane. In some embodiments, the synthetic polymer membrane is microporous. The printed circuit may be discontinuously bonded to the stretchable or non-stretchable substrate by adhesive dots (620). The printed circuits may be integrated into garments, such as smart apparel or other wearable technology.
    Type: Grant
    Filed: May 8, 2019
    Date of Patent: May 10, 2022
    Assignee: W. L. Gore & Associates, Inc.
    Inventors: Mark D. Edmundson, Paul D. Gassler, Justin J. Skaife, Scott J. Zero
  • Patent number: 11328835
    Abstract: A conductive pattern having high dispersion stability and a low resistance over a board is formed. A dispersing element (1) contains a copper oxide (2), a dispersing agent (3), and a reductant. Content of the reductant is in a range of a following formula (1). Content of the dispersing agent is in a range of a following formula (2). 0.0001?(reductant mass/copper oxide mass)?0.10??(1) 0.0050?(dispersing agent mass/copper oxide mass)?0.30??(2) The dispersing element containing the reductant promotes reduction of copper oxide to copper in firing and promotes sintering of the copper.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: May 10, 2022
    Assignee: Asahi Kasei Kabushiki Kaisha
    Inventors: Eiichi Ohno, Toru Yumoto, Masanori Tsuruta
  • Patent number: 11315865
    Abstract: A method of manufacturing circuit board structure includes forming a sacrificial layer having first openings on a substrate; forming a metal layer on the sacrificial layer; forming a patterned photoresist layer having second openings over the sacrificial layer, in which the second openings are connected to the first openings and expose a portion of the metal layer; forming a first circuit layer filling the second openings and the first openings; forming a first dielectric layer over the sacrificial layer and covering the metal layer, in which the first dielectric layer has third openings exposing the first circuit layer; forming a second circuit layer filling the third openings and covering a portion of the first dielectric layer; removing the substrate to expose the sacrificial layer, a portion of the metal layer and a portion of the first circuit layer; and removing the sacrificial layer and the metal layer.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: April 26, 2022
    Assignee: Unimicron Technology Corp.
    Inventor: Chien-Chen Lin
  • Patent number: 11310922
    Abstract: A board-to-board connecting structure which adds no significant thickness to a single printed circuit board includes a first circuit board and a second circuit board. The first circuit board includes first circuit substrate, adhesive layer, and second circuit substrate. The first circuit substrate includes first base layer, first inner wiring layer with first pad, and first outer wiring layer defining a receiving space. The second circuit substrate includes insulating layer and two second outer wiring layers. A conductive via in the second circuit substrate connects the two second outer wiring layers. The second circuit board includes second base layer and also two third outer wiring layers each with a second pad. The second circuit board is laterally disposed in the receiving space and one second pad connects to the conductive via and the other to the first pad.
    Type: Grant
    Filed: September 22, 2020
    Date of Patent: April 19, 2022
    Assignees: Avary Holding (Shenzhen) Co., Limited., QING DING PRECISION ELECTRONICS (HUAIAN) CO., LTD
    Inventors: Rui-Wu Liu, Man-Zhi Peng
  • Patent number: 11310915
    Abstract: A method of manufacturing a curved electronic device (100) and resulting product. A patterned layer of non-conductive support material (12m) is printed onto a thermoplastic substrate (11) to form a support pattern. An electrical circuit (13,14) is applied onto the support pattern (12), wherein the electrical circuit (13,14) comprises circuit lines (13) comprising a conductive material (13m) applied onto support lines (12b) of the pattern and electrical components (14) applied onto support islands (12a) of the pattern. A thermoforming process (P) is used for deforming (S) the substrate (11) while a relatively high resistance of the support material (12m) to the deforming maintains a structural integrity of the electrical circuit (13,14).
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: April 19, 2022
    Assignee: Nederlandse Organisatie voor toegepast-natuurwetenschappelijk onderzoek TNO
    Inventors: Edsger Constant Pieter Smits, Jan-Eric Jack Martijn Rubingh, Marco Barink
  • Patent number: 11304324
    Abstract: A method of assembling a hermetically sealed printed circuit board includes: securing a flange of a cap against an electrical contact region on a first side of a substrate, the flange extending across a first end portion of a wall of the cap, the wall extending around the electrical contact region and including a second end portion disposed in an open configuration; and closing the second end portion of the wall to form a hermetically sealed chamber around the electrical contact region.
    Type: Grant
    Filed: March 30, 2021
    Date of Patent: April 12, 2022
    Assignee: COVIDIEN LP
    Inventor: Anthony Sgroi, Jr.
  • Patent number: 11304296
    Abstract: A substrate is provided. The substrate includes a bottom plate and at least one bonding portion disposed on the bottom plate, where each bonding portion takes a shape that is a part of an Archimedean spiral. An electronic device, a bonding structure, and a bonding method for the bonding structure are further provided.
    Type: Grant
    Filed: April 28, 2018
    Date of Patent: April 12, 2022
    Assignee: SHENZHEN ROYOLE TECHNOLOGIES CO., LTD.
    Inventors: Zhigao Xu, Hewen Shen
  • Patent number: 11304295
    Abstract: In order to provide a mounting structure that has high reliability and easily follows a curved surface, the mounting structure includes a flexible circuit board, a non-flexible component, and a connection portion that is provided in a region smaller than a bottom surface of the non-flexible component and connects the flexible circuit board and the non-flexible component to each other. Further, a protection resin that seals the connection portion in such a way that the flexible circuit board and the non-flexible component are separable from each other outside of the connection portion, is provided. In this configuration, the protection resin covers only a region provided with the connection portion. Thus, the connection portion is mechanically reinforced by the protection resin, and is protected from moisture and dust. Further, on an outside of the connection portion, the flexible circuit board can be bent.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: April 12, 2022
    Assignee: NEC Corporation
    Inventor: Kyoko Otsuka
  • Patent number: 11297720
    Abstract: A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.
    Type: Grant
    Filed: April 21, 2021
    Date of Patent: April 5, 2022
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Yun Mi Bae, Soon Gyu Kwon, Sang Hwa Kim, Sang Young Lee, Jin Hak Lee, Han Su Lee, Dong Hun Jeong, In Ho Jeong, Dae Young Choi, Jung Ho Hwang
  • Patent number: 11297714
    Abstract: A printed circuit board includes a first insulating layer, an embedded pattern embedded in one surface of the first insulating layer, a pad formed on the one surface of the first insulating layer, and a post, wherein the center of a side surface of the post is in contact with the one surface of the first insulating layer.
    Type: Grant
    Filed: October 14, 2020
    Date of Patent: April 5, 2022
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Young-Kuk Ko, Yoong Oh, Sang-Hoon Kim, Gyu-Mook Kim, Yong-Soon Jang, Hea-Sung Kim
  • Patent number: 11291114
    Abstract: This fiber net includes a fiber net having an electrode part, in which a fiber constituting the electrode part includes a core material, a relaxation layer which covers at least a part of a surface of the core material and contains a material having a higher Young's modulus than a material forming the core material, and a conductive layer which covers a surface of the relaxation layer on a side opposite to the core material side.
    Type: Grant
    Filed: March 13, 2019
    Date of Patent: March 29, 2022
    Assignee: JAPAN SCIENCE AND TECHNOLOGY AGENCY
    Inventors: Takao Someya, Sunghoon Lee
  • Patent number: 11277906
    Abstract: The invention provides a printed circuit board (10) including a first electrically conductive track (210), wherein the printed circuit board (10) comprises a set (15) of two printed circuit board areas (100) both comprising a part of the first electrically conductive track (210), wherein printed circuit board (10) further comprises a perforation line (300) between the two printed circuit board areas (100) for customizing the printed circuit board (10) into two physically separated printed circuit board area comprising parts (1100), wherein the perforation line (300) is configured as a non-straight line, wherein the perforation line (300) comprises relative to one of the printed circuit board areas (100), and in a plane of the printed circuit board (10), a first projecting part (311) and a first recessed part (312), wherein the first recessed part (312) is recessed relative to the first projecting part (311), wherein the first electrically conductive track (210) is intercepted by the perforation line (300) at
    Type: Grant
    Filed: October 7, 2019
    Date of Patent: March 15, 2022
    Assignee: SIGNIFY HOLDING B.V.
    Inventors: Remco Christianus Wilhelmus Leermakers, Frank Walterus Marie Van Kempen
  • Patent number: 11277904
    Abstract: The disclosure discloses a circuit board, as well as a backlight module and a display device including the circuit board. The circuit board includes a copper exposure region which is covered with a conductive ink. By means of the copper exposure region and the conductive ink thereon, the function of conducting electrostatic charges for the circuit board can be realized at low cost in high efficiency, thereby reducing the risk of subjecting the electrical elements on the circuit board to electrostatic breakdown.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: March 15, 2022
    Assignees: BOE TECHNOLOGY GROUP CO., LTD., CHONGQING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD.
    Inventors: Xuefeng Wang, Guohui Chen, Hang Min, Qiangsheng Han, Wei Chen
  • Patent number: 11270809
    Abstract: A conductive pattern having high dispersion stability and a low resistance over a board is formed. A dispersing element (1) contains a copper oxide (2), a dispersing agent (3), and a reductant. Content of the reductant is in a range of a following formula (1). Content of the dispersing agent is in a range of a following formula (2). 0.0001?(reductant mass/copper oxide mass)?0.10??(1) 0.0050?(dispersing agent mass/copper oxide mass)?0.30??(2) The dispersing element containing the reductant promotes reduction of copper oxide to copper in firing and promotes sintering of the copper.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: March 8, 2022
    Assignee: Asahi Kasei Kabushiki Kaisha
    Inventors: Eiichi Ohno, Toru Yumoto, Masanori Tsuruta
  • Patent number: 11272614
    Abstract: A printed wiring board includes a base insulating layer, a conductor layer formed on the base insulating layer and having a conductor pad, a solder resist layer formed on the base insulating layer such that the solder resist layer is covering the conductor layer and has an opening exposing the conductor pad in the conductor layer, and a bump formed on the conductor pad of the conductor layer and including a base plating layer formed in the opening of the solder resist layer, an intermediate layer formed on the base plating layer, and a top plating layer formed on the intermediate layer such that that the base plating layer has a side surface exposed from the solder resist layer and that the intermediate layer has a side surface protruding from the side surface of the base plating layer.
    Type: Grant
    Filed: October 27, 2020
    Date of Patent: March 8, 2022
    Assignee: IBIDEN CO., LTD.
    Inventor: Satoru Kawai
  • Patent number: 11266024
    Abstract: An elongated wired circuit board including a plurality of wires arranged in parallel, wherein the plurality of wires each includes a first linear portion extending in a first linear direction, a second linear portion extending in a second linear direction, and a connection portion, the connection portion includes a first side, a second side, a third side, and a fourth side, length y1 and length S satisfy 0<y1<S, length y1 extending from the first corner portion reaching the first widthwise other end edge of the first linear portion, and length S extending from the first widthwise other end edge of the first linear portion of one wire, and the predetermined angle ? satisfies 0<?<1 deg.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: March 1, 2022
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shusaku Shibata, Takahiro Takano, Hayato Takakura, Yoshihiro Kawamura, Shuichi Wakaki