Patents Examined by Jeremy C. Norris
  • Patent number: 10938128
    Abstract: Superconducting interconnects with ultra-low thermal conductivity capable of providing a direct connection between a millikelvin temperature environment and a 70 K temperature environment.
    Type: Grant
    Filed: May 1, 2020
    Date of Patent: March 2, 2021
    Assignee: Brookhaven Technology Group, Inc.
    Inventor: Vyacheslav Solovyov
  • Patent number: 10939545
    Abstract: A foldable modular flex circuit for attaching to at least one component. The flex circuit may comprise a central area and at least one tab depending from the central area. The central area may comprise a cable attachment section configured to electrically couple to at least one coaxial cable. A first tab may depend from the central area and is configured to electrically couple to a ball grid array (BGA) of the component. A second pair of tabs may depend from the central area and are configured to electrically couple to an additional at least one component, wherein each tab depends substantially perpendicular from the central area.
    Type: Grant
    Filed: February 10, 2020
    Date of Patent: March 2, 2021
    Assignee: High Speed Interconnects, LLC
    Inventors: Antonio De La Rosa, Todd Albertson
  • Patent number: 10939563
    Abstract: A method of manufacturing a constituent for a component carrier is disclosed. The method includes providing an electrically conductive structure, forming a highly thermally conductive and electrically insulating or semiconductive structure on the electrically conductive structure, and subsequently, attaching a thermally conductive and electrically insulating structure, having a lower thermal conductivity than the highly thermally conductive and electrically insulating or semiconductive structure, on an exposed surface of the highly thermally conductive and electrically insulating or semiconductive structure.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: March 2, 2021
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Jonathan Silvano De Sousa, Markus Leitgeb
  • Patent number: 10939561
    Abstract: A wiring structure includes a first dielectric layer, a second dielectric layer adjacent to the first dielectric layer, and a conductive region. The first dielectric layer defines a first opening, and the second dielectric layer defines a second opening. The conductive region includes a conductive via filling the first opening and the second opening. The conductive region further includes a first conductive trace embedded in the second dielectric layer and electrically connected with the conductive via. The conductive region includes a sidewall traversing through a thickness of the second dielectric layer with a substantial linear profile. A method of manufacturing a wiring structure is also disclosed.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: March 2, 2021
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Wen Hung Huang, Min Lung Huang
  • Patent number: 10925162
    Abstract: A printed circuit board is provided. The printed circuit board includes N power layers and a first via group. The N power layers are arranged in parallel and spaced from each other. The first via group includes M rows of vias which are disposed through the N power layers, where N and M are positive integers greater than 0. Each row of the M rows of vias is electrically connected to the first layer of the N power layers. A Pth row of the M rows of vias is further electrically connected to Q power layers of the N power layers respectively, where Q is a smallest positive integer greater than or equal to P((N?1)/M), and P is a positive integer less than or equal to M.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 16, 2021
    Assignee: Wiwynn Corporation
    Inventors: Cheng Fu Hsu, Cheng Wei Lin, Ting-Kai Wang
  • Patent number: 10917968
    Abstract: Package to printed circuit board (PCB) transitions are described. In one aspect, a multi-layer PCB includes an external layer having a transition region configured to receive an electrical component and a clear routing region outside of the transition region. The PCB includes first via(s) that extend from the transition region to an inner trace routing layer. The trace routing layer is disposed between the external layer and the second inner trace routing layer. The first inner trace routing layer includes a transition area disposed under the transition region of the external layer, a clear routing area outside of the transition region, and a transmission line that connects a given first via to a second via for a second electrical component. The transmission line includes conductive trace(s) that each have a first width in the transition area and a second width, greater than the first width, in the clear routing area.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: February 9, 2021
    Assignee: Google LLC
    Inventor: Leesa Marie Noujeim
  • Patent number: 10905013
    Abstract: In a wiring base body of a printed wiring board, a conductive post including a wiring portion and a wiring are embedded in an insulating resin film. Therefore, even in a region in which a wiring portion is formed, the wiring base body is not increased in thickness. In addition, even in a region in which a wiring is formed, the wiring base body is not increased in thickness. Therefore, it is possible to obtain a printed wiring board having high flatness by stacking a plurality of wiring base bodies and constituting a printed wiring board.
    Type: Grant
    Filed: May 24, 2019
    Date of Patent: January 26, 2021
    Assignee: TDK CORPORATION
    Inventors: Takaaki Morita, Seiichi Tajima, Takashi Kariya
  • Patent number: 10897809
    Abstract: To achieve heat dissipation of a wiring pattern inexpensively with a simple configuration, a printed circuit board includes an insulating substrate having a plurality of wiring patterns on a main surface thereof, and an electronic component mounted on the main surface and connected to the wiring patterns. Further, the printed circuit board includes a heat-dissipating surface mount component that is a surface mount component. The heat-dissipating surface mount component is joined via a solder to each of the wiring patterns on the main surface to dissipate heat of the wiring pattern.
    Type: Grant
    Filed: December 16, 2016
    Date of Patent: January 19, 2021
    Assignee: Mitsubishi Electric Corporation
    Inventors: Tsuyoshi Miura, Masahiro Koyama
  • Patent number: 10897812
    Abstract: A component carrier and a method of manufacturing the same are disclosed. The component carrier has a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, and a component embedded in the stack. Sidewalls of the component are directly covered with an electrically conductive layer. The component carrier achieves enhanced thermal dissipation and EMI shielding characteristics and has an improved stiffness.
    Type: Grant
    Filed: December 24, 2019
    Date of Patent: January 19, 2021
    Assignee: AT&S (Chongqing) Company Limited
    Inventor: Minwoo Lee
  • Patent number: 10893607
    Abstract: A microcapsule includes a shell including a conducting component, and a thermally expandable component contained in the shell and having a property of expanding by heating. The shell is deformable in accordance with expansion of the thermally expandable component when the thermally expandable component is heated.
    Type: Grant
    Filed: March 9, 2020
    Date of Patent: January 12, 2021
    Assignee: CASIO COMPUTER CO., LTD.
    Inventors: Kenji Iwamoto, Satoshi Kurosawa
  • Patent number: 10889086
    Abstract: A resin film according to one aspect of the present invention is a resin film having polyimide as a main component, the resin film including a modified layer formed in a depth direction from at least one side of the resin film; and a non-modified layer other than the modified layer, wherein a ring-opening rate of an imide ring of the polyimide in the modified layer is higher than a ring-opening rate of an imide ring of the polyimide in the non-modified layer, and an average thickness of the modified layer from the one side of the resin film is greater than or equal to 10 nm and less than or equal to 500 nm.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: January 12, 2021
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Kayo Hashizume, Yoshio Oka, Masamichi Yamamoto, Takashi Kasuga, Yugo Kubo, Hideki Kashihara, Hiroshi Ueda
  • Patent number: 10882737
    Abstract: A through silicon interposer wafer and method of manufacturing the same. A through silicon interposer wafer having at least one cavity formed therein for MEMS applications and a method of manufacturing the same are provided. The through silicon interposer wafer includes one or more filled silicon vias formed sufficiently proximate to the at least one cavity to provide support for walls of the at least one cavity during subsequent processing of the interposer wafer.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: January 5, 2021
    Assignee: Agency for Science, Technology and Research
    Inventors: Navab Singh, Daw Don Cheam
  • Patent number: 10884564
    Abstract: The present invention relates to a thin plate shaped apparatus comprising a plurality of first electrodes and a plurality of second electrodes which are arranged on the first surface of a nonconductive base material, a linear conductive member, a plurality of indicator electrodes formed in the operation area.
    Type: Grant
    Filed: March 20, 2018
    Date of Patent: January 5, 2021
    Assignee: I.P SOLUTIONS, LTD
    Inventor: Kenji Yoshida
  • Patent number: 10887986
    Abstract: A printed circuit board includes an insulating layer, a pad, and a via fill. The insulating layer includes a via hole. The pad is formed in the insulating layer such that an intermediate portion thereof is exposed by the via hole. The pad includes a through hole formed in the intermediate portion. The via fill is formed in the via hole, configured to fill the through hole, and coupled to the intermediate portion.
    Type: Grant
    Filed: November 7, 2019
    Date of Patent: January 5, 2021
    Assignee: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Mi-Sun Hwang, Sun-A Kim
  • Patent number: 10881006
    Abstract: A package carrier includes a plurality of first circuit patterns, a plurality of second circuit patterns and an insulating material layer. The second circuit patterns are disposed between any two the first circuit patterns and are directly connected to the first circuit patterns. In a cross-sectional view, a first thickness of each of the first circuit patterns is greater than a second thickness of each of the second circuit patterns. A first surface of each of the first circuit patterns is aligned with a second surface of each of the second circuit patterns. The insulating material layer at least contacts the first circuit patterns.
    Type: Grant
    Filed: January 10, 2020
    Date of Patent: December 29, 2020
    Assignee: Unimicron Technology Corp.
    Inventors: Ra-Min Tain, Pei-Chang Huang, Chi-Chun Po, Chun-Lin Liao, Po-Hsiang Wang, Hsuan-Wei Chen
  • Patent number: 10880997
    Abstract: Disclosed is a stretchable member with a metal foil including a stretchable resin base material, and a conductive metal foil provided on the stretchable resin base material. A surface of the metal foil on the stretchable resin base material side is a roughened surface having surface roughness Ra of 0.1 ?m to 3 ?m.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 29, 2020
    Assignee: SHOWA DENKO MATERIALS CO., LTD.
    Inventors: Tangyii Sim, Kumpei Yamada, Takashi Kawamori, Takeshi Masaki
  • Patent number: 10880992
    Abstract: A circuit board structure including a dielectric substrate having a plurality of vias, a first conductor layer, a second conductor layer, an insulating layer, and a third conductor layer. The first and the second conductor layers are disposed at opposite surfaces of the dielectric substrate. The first conductor layer forms a plurality of traces including at least one high-speed differential pair and a plurality of ground traces, wherein the vias are located on the ground traces. The electric insulated layer is disposed on the dielectric substrate and covers the first conductor layer, and the third conductor layer is disposed on the insulating layer.
    Type: Grant
    Filed: July 26, 2019
    Date of Patent: December 29, 2020
    Assignee: Advanced Connectek Inc.
    Inventors: Min-Lung Chien, Mao-Sheng Chen, Wen-Yu Wang
  • Patent number: 10880993
    Abstract: A circuit board includes a substrate, a first measurement mark and a second measurement mark, the first and second measurement marks are located on a predetermined punch area of the substrate. After punching, the predetermined punch area is removed such that the circuit board has a through hole and a sheet is separated from the circuit board. By the first and second measurement marks on the sheet, a first distance between a first edge of the sheet and the first measurement mark and a second distance between a second edge of the sheet and the second measurement mark can be measured to determine whether the through hole is shifted or has an incorrect size.
    Type: Grant
    Filed: June 24, 2020
    Date of Patent: December 29, 2020
    Assignee: CHIPBOND TECHNOLOGY CORPORATION
    Inventors: Yi-Chen Lien, Yen-Ping Huang, Hui-Yu Huang, Chih-Ming Peng, Chun-Te Lee
  • Patent number: 10881000
    Abstract: A printed circuit board includes a core layer having a first surface and a second surface opposing the first surface; a first built-up structure disposed on the first surface of the core layer; a second built-up structure disposed on the second surface of the core layer; and a first penetration portion penetrating the first built-up structure and the core layer and penetrating a portion of the second built-up structure. The first penetration portion has a step portion on at least a portion of a wall of the first penetration portion in the region of the first penetration portion penetrating the second built-up structure, and a region including the first penetration portion on a plane is configured as a flexible region.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: December 29, 2020
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Yang Je Lee, Hyun Kyung Park, Jung Hoon Jang
  • Patent number: 10863631
    Abstract: A manufacturing method, wherein the method includes providing a layer stack having at least partially uncured component carrier material, arranging a plurality of components in recesses of the layer stack, integrally connecting the components with the layer stack by curing the component carrier material, and applying a high temperature robust dielectric structure on a main surface of the cured layer stack with the components therein.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: December 8, 2020
    Assignee: AT&S Austria Technologie & Systemtechnik Aktiengesellschaft
    Inventors: Johannes Stahr, Timo Schwarz, Mario Schober