Patents Examined by Jeremy C. Norris
  • Patent number: 11930586
    Abstract: A wiring substrate includes: an insulating substrate including a base portion comprising a through hole having a first opening and a second opening, and a frame portion located on the base portion; and a heat dissipator disposed on a side of the base portion that is opposite to the frame portion so as to block the second opening, wherein an inner surface of the through hole faces a side surface of the heat dissipator with a clearance being provided between the inner surface of the through hole and the side surface of the heat dissipator.
    Type: Grant
    Filed: February 10, 2023
    Date of Patent: March 12, 2024
    Assignee: KYOCERA Corporation
    Inventor: Toshiyuki Hamachi
  • Patent number: 11930591
    Abstract: According to one embodiment, a flexible substrate includes a support plate including a first surface, a line portion located on the first surface and including a first side surface and a second side surface on an opposite side to the first side surface and a protective member which covers the line portion, in contact with the first surface. The line portion includes a flexible insulating base located on the first surface and a wiring layer disposed on the insulating base, the protective member is separated from at least a part of the first side surface via an air layer and from at least a part of the second side surface via an air layer, and the air layers extend along the line portion.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: March 12, 2024
    Assignee: Japan Display Inc.
    Inventor: Takumi Sano
  • Patent number: 11924965
    Abstract: A package component and forming method thereof are provided. The package component includes a substrate and a conductive layer. The substrate includes a first surface. The conductive layer is disposed over the first surface. The conductive layer includes a first conductive feature and a second conductive feature. The second conductive feature covers a portion of the first conductive feature. A resistance of the second conductive feature is lower than a resistance of the first conductive feature.
    Type: Grant
    Filed: April 25, 2022
    Date of Patent: March 5, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chun-Wei Chang, Jian-Hong Lin, Shu-Yuan Ku, Wei-Cheng Liu, Yinlung Lu, Jun He
  • Patent number: 11924960
    Abstract: Provided is a circuit board on which a circuit component is mounted on one side, and a recess is formed at a position corresponding to the circuit component on the other side, and the circuit board includes a first heat conductive member that is provided inside the recess and conducts heat generated by the circuit component.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: March 5, 2024
    Assignees: AutoNetworks Technologies, Ltd., Sumitomo Wiring Systems, Ltd., Sumitomo Electric Industries, Ltd.
    Inventor: Akira Haraguchi
  • Patent number: 11917758
    Abstract: A substrate structure, a manufacturing method thereof, and an electronic device. The substrate structure includes a substrate, conductive wires and conductive members. Multiple through holes penetrate through the substrate body of the substrate. Multiple first conductive pads are arranged on the first surface of the substrate body. Multiple second conductive pads are arranged on the second surface of the substrate body. The conductive wires are accommodated in the through holes and each has a first end in the first opening of corresponding through hole and a second end in the second opening of corresponding through hole. The conductive members are distributed on the first and second surfaces, and both ends thereof are connected to the corresponding first and second conductive pads through the conductive members. At least part of each conductive wire does not contact the hole wall of each through hole in a direct manner.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: February 27, 2024
    Assignee: PANELSEMI CORPORATION
    Inventor: Ya-Che Hsueh
  • Patent number: 11917746
    Abstract: A method of forming a heat spreader on a printed circuit board (PCB), having a power dissipating component operably coupled thereto, includes attaching a thermally and electrically conductive structure, to a first side of the PCB to define a first PCB region that includes the component and a second PCB region without. The underside of the component is underfilled to electrically insulate its solder contacts. A first protective layer is applied to the second region of the PCB. A conductive plating membrane is deposited to the first region, the second region, and to the structure. A second protective layer is applied over a portion of the conductive plating membrane that overlays the second region, leaving exposed the rest of the conductive plating membrane. An electrically and thermally conductive layer is electroplated over the exposed areas of the conductive plating membrane, to form a heat exchanger within the first region.
    Type: Grant
    Filed: April 22, 2022
    Date of Patent: February 27, 2024
    Assignee: Raytheon Company
    Inventors: Miroslav Micovic, Brandon W. Pillans, Andrew D. Gamalski, Andrew K. Brown
  • Patent number: 11917784
    Abstract: A fixing device includes a circuit board, an insertion slot, and a fixing bracket. The circuit board has a peripheral recess, and the insertion slot is disposed on the circuit board. The fixing bracket is fixed in the peripheral recess, and the fixing bracket has a board, two lateral arms, and two guiding rails. The two lateral arms are connected to two corresponding sides of the board, and the two lateral arms are integrally formed from the board. In addition, the two guiding rails are respectively disposed at the two lateral arms, in which the two guiding rails extend towards the insertion slot.
    Type: Grant
    Filed: June 10, 2022
    Date of Patent: February 27, 2024
    Assignees: Inventec (Pudong) Technology Corporation, INVENTEC CORPORATION
    Inventors: Chi-Yu Huang, Hsu-Kai Tsai
  • Patent number: 11916285
    Abstract: A wiring board (10) includes a substrate (11) that is transparent and a wiring pattern region (20) that is disposed on the substrate (11) and that includes a plurality of wiring lines (21, 22). The wiring pattern region (20) has a sheet resistance of less than or equal to 5 ?/sq, and each wiring line (21, 22) has a maximum width of less than or equal to 3 ?m when viewed at a viewing angle of 120°.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: February 27, 2024
    Assignee: Dai Nippon Printing Co., Ltd.
    Inventors: Koichi Suzuki, Seiji Take, Daisuke Matsuura
  • Patent number: 11908786
    Abstract: A wiring structure includes a test pattern layer. The test pattern layer includes a test circuit pattern and a heat dissipating structure. The heat dissipating structure is disposed adjacent to the test circuit pattern, and is configured to reduce temperature rise of the test circuit pattern when a power is applied to the test circuit pattern.
    Type: Grant
    Filed: February 18, 2022
    Date of Patent: February 20, 2024
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Ting Wei Hsu
  • Patent number: 11910521
    Abstract: Disclosed herein are apparatus and methods for a power electronics assembly that includes a printed circuit board (PCB) and an electrical insulation portion. The PCB includes a plurality of embedded power devices and a substrate layer having a plurality of metal inverse opal (MIO) portions. The electrically insulating portion is positioned between each of the MIO portions. The plurality of MIO portions is thermally coupled to the plurality of embedded power devices.
    Type: Grant
    Filed: March 21, 2022
    Date of Patent: February 20, 2024
    Assignee: TOYOTA MOTOR ENGINEERING & MANUFACTURING NORTH AMERICA, INC.
    Inventors: Feng Zhou, Ercan Dede, Hiroshi Ukegawa
  • Patent number: 11903133
    Abstract: A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.
    Type: Grant
    Filed: September 29, 2022
    Date of Patent: February 13, 2024
    Assignee: ZHUHAI ACCESS SEMICONDUCTOR CO., LTD
    Inventors: Xianming Chen, Lei Feng, Gao Huang, Benxia Huang, Yejie Hong
  • Patent number: 11903128
    Abstract: A wiring substrate includes an insulating layer, a conductor layer formed on a surface of the insulating layer such that the conductor layer includes a conductor pad, and a solder resist layer formed on the surface of the insulating layer such that the solder resist layer is covering the conductor layer and having an opening exposing the conductor pad. The conductor pad of the conductor layer has a substantially rectangular planar shape such that the conductor pads has a main surface, a pair of long sides, a pair of short sides and four corner portions, and the solder resist layer is formed such that the opening is exposing side surfaces at the long sides and 50% or more of the main surface and that the solder resist layer is covering side surfaces at the short sides.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: February 13, 2024
    Assignee: IBIDEN CO., LTD.
    Inventor: Shigeto Iyoda
  • Patent number: 11895778
    Abstract: An etching method for manufacturing a substrate structure having a thick electrically conductive layer, and a substrate structure having a thick electrically conductive layer are provided.
    Type: Grant
    Filed: December 16, 2021
    Date of Patent: February 6, 2024
    Assignee: AMULAIRE THERMAL TECHNOLOGY, INC.
    Inventors: Shih-Hsi Tai, Tung-Ho Tao, Tze-Yang Yeh
  • Patent number: 11894164
    Abstract: A stretchable conductor includes a substrate with a first major surface, wherein the substrate is an elastomeric material. An elongate wire is on the first major surface of the substrate; the wire includes a first end and a second end, and further includes at least one arcuate region between the first end and the second end. At least one portion of the arcuate region of the wire in the region has a first surface area portion embedded in the surface of the substrate and a second surface area portion unembedded on the substrate and exposed in an amount sufficient to render at least an area of the substrate in the region electrically conductive. The unembedded second surface portion of the arcuate region may lie above or below a plane of the substrate. Composite articles including a stretchable conductor in durable electrical contact with a conductive fabric are also disclosed.
    Type: Grant
    Filed: September 23, 2020
    Date of Patent: February 6, 2024
    Assignee: 3M INNOVATIVE PROPERTIES COMPNAY
    Inventors: Ankit Mahajan, James Zhu, Saagar A. Shah, Mikhail L. Pekurovsky, Vivek Krishnan, Kevin T. Reddy, Christopher B. Walker, Jr., Michael A. Kropp, Kara A. Meyers, Teresa M. Goeddel, Thomas J. Metzler, Jonathan W. Kemling, Roger W. Barton
  • Patent number: 11889622
    Abstract: An electronic device includes a component carrier having a stack with at least one electrically conductive layer structure and/or at least one electrically insulating layer structure, an electronic component on and/or in the stack, and a cooling member with a fluid cooling unit at least partially therein. The component carrier and the cooling member are connected by a connection structure.
    Type: Grant
    Filed: February 8, 2022
    Date of Patent: January 30, 2024
    Assignee: AT&S Austria Technologie & Systemtechnik AG
    Inventor: Gerald Weis
  • Patent number: 11889617
    Abstract: A printed circuit board includes first and second surfaces, first and second layers, and first and second vias. The first via extends from a first layer to the second surface and includes a first portion that is on a conductive path between the first layer and the second layer and a second portion that is not on the conductive path. A length of the first portion of the first via is greater than that of the second portion of the first via. The second via extends from the second surface to the second layer. The second via includes a first portion that is on the conductive path between the first layer and the second layer and a second portion that is not on the conductive path. A length of the first portion of the second via is greater than that of the second portion of the second via.
    Type: Grant
    Filed: September 1, 2022
    Date of Patent: January 30, 2024
    Assignee: BAIDU USA LLC
    Inventors: Zhenwei Yu, Yun Ji
  • Patent number: 11877385
    Abstract: A circuit board comprises a substrate with opposite first and second sides. A pair of plated through holes (PTHs) extends along z-axis. A pair of signal traces are made on the first side of the substrate and electrically coupled to the pair of the PTHs respectively to form a differential pair. A ground metal is made on the second side of the substrate, the ground metal has a clearance made therein. The ground metal extends fully overlapping with the full signal traces to eliminate reflection noise caused by a boundary between the clearance and the metal ground.
    Type: Grant
    Filed: July 14, 2022
    Date of Patent: January 16, 2024
    Assignee: FIRST HI-TEC ENTERPRISE CO., LTD.
    Inventors: Ching-Shan Chang, Kun-Tao Tang, Tsung-Ting Tsai, Chien-Lin Chen
  • Patent number: 11877397
    Abstract: The printed circuit board includes, a first conductive layer including copper foil, an insulating base layer, and a second conductive layer including copper foil in this order, and includes a via-hole laminate that is stacked on an inner circumference and a bottom of a connection hole extending through the first conductive layer and the base layer in a thickness direction. The via-hole laminate has an electroless copper plating layer stacked on the connection hole and an electrolytic copper plating layer stacked on the electroless copper plating layer. The copper foil has copper crystal grains oriented in a (100) plane orientation, and an average crystal grain size of copper of 10 ?m or more. The electroless copper plating layer includes palladium and tin, and an amount of the palladium stacked per unit area of a surface of the copper foil is 0.18 ?g/cm2 or more and 0.40 ?g/cm2 or less.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: January 16, 2024
    Assignees: SUMITOMO ELECTRIC INDUSTRIES, LTD., SUMITOMO ELECTRIC PRINTED CIRCUITS, INC.
    Inventors: Junichi Motomura, Koji Nitta, Shoichiro Sakai, Mari Sogabe, Mitsutaka Tsubokura, Akira Tsuchiko, Masashi Iwamoto
  • Patent number: 11877389
    Abstract: An apparatus with an anti-tamper architecture includes a substrate and a layer of a pyrotechnic composite arranged on a surface of the substrate. The pyrotechnic composite includes a metal and a metal oxide, and the layer has a thickness of about 1 micrometer to about 10 millimeters. A reaction of the pyrotechnic composite is an exothermic reaction and at least partially fractures the substrate after the reaction is initiated.
    Type: Grant
    Filed: December 14, 2020
    Date of Patent: January 16, 2024
    Assignee: ROCKWELL COLLINS, INC.
    Inventors: Mark Andrew Schoelen, Thomas Michael Deppert, Reginald Bean
  • Patent number: 11877391
    Abstract: An object of the present invention is to provide a conductive film that is excellent in flexibility while maintaining its sufficient transparency and conductivity, and a conductive film roll, an electronic paper, a touch panel, and a flat-panel display having the same. A conductive film having a transparent substrate and a conductive part having a fine metal wire pattern disposed on one side or both sides of the transparent substrate, wherein the fine metal wire pattern is constituted by a fine metal wire, and the conductive film satisfies the following condition (i) or (ii): (i) the fine metal wire has voids, and when the cross-sectional area of the fine metal wire is defined as SM and the total cross-sectional area of the voids included in the cross-section of the fine metal wire is defined as SVtotal on the cross-section of the fine metal wire perpendicular to the direction of drawing of the fine metal wire, SVtotal/SM is 0.10 or more and 0.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: January 16, 2024
    Assignee: ASAHI KASEI KABUSHIKI KAISHA
    Inventors: Takeshi Kamijo, Sora Hida, Tetsuro Sugimoto, Yu Tomono