Patents Examined by Jeremy C. Norris
  • Patent number: 10383219
    Abstract: In embodiments, the present invention may attach at least two isolated electronic components to an elastomeric substrate, and arrange an electrical interconnection between the components in a boustrophedonic pattern interconnecting the two isolated electronic components with the electrical interconnection. The elastomeric substrate may then be stretched such that the components separate relative to one another, where the electrical interconnection maintains substantially identical electrical performance characteristics during stretching, and where the stretching may extend the separation distance between the electrical components to many times that of the unstretched distance.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: August 13, 2019
    Assignee: MC10, Inc.
    Inventors: William J. Arora, Roozbeh Ghaffari
  • Patent number: 10375818
    Abstract: An objective of the present invention is to provide a printed board being capable of suppressing EMI emissions from power supply wirings. To accomplish the objective, a printed board of the present invention includes a plurality of ground layers disposed in a printed board, a power supply layer put between the plurality of the ground layers, and through holes disposed along at least periphery of the printed board and connecting the plurality of the ground layers, wherein the through holes are disposed at intervals according to a wavelength corresponding to a maximum frequency of electromagnetic waves to be suppressed.
    Type: Grant
    Filed: July 4, 2016
    Date of Patent: August 6, 2019
    Assignee: NEC CORPORATION
    Inventors: Kazuhiro Kashiwakura, Ayako Uemura
  • Patent number: 10362670
    Abstract: An electronic device such as a cover for a portable device may be provided with a body having hinge portions. The hinge portions may allow the body to bend about one or more bend axes. The cover may have electrical components such as a keyboard. A keyboard may be mounted at one end of the cover and a connector may be mounted at an opposing end of the cover. A flexible fabric signal path structure may be formed from metal traces on a flexible fabric substrate. At one end of the cover, the flexible fabric signal path structure may be coupled to a printed circuit in the keyboard using conductive adhesive. At the opposing end of the cover, the metal traces on the flexible fabric substrate may be coupled to the connector.
    Type: Grant
    Filed: January 29, 2018
    Date of Patent: July 23, 2019
    Assignee: Apple Inc.
    Inventors: Benjamin A. Cousins, Kurt R. Stiehl, Samuel G. Smith, Kirk M. Mayer, Siddhartha Hegde, Melody Kuna
  • Patent number: 10359685
    Abstract: A three-dimensional circuit includes a hyperbolic bicontinuous structure forming a substrate; circuits formed on a first surface of the hyperbolic bicontinuous structure; and electrically conductive traces formed between the circuits. The electrically conductive traces are formed two-dimensionally on the first surface of the hyperbolic bicontinuous structure. The electrically conductive traces are effectively three-dimensional traces between the circuits.
    Type: Grant
    Filed: September 14, 2015
    Date of Patent: July 23, 2019
    Inventor: Robert William Corkery
  • Patent number: 10362675
    Abstract: Disclosed is a flexible circuit board having a three-layer dielectric body and four-layer ground layer structure. A flexible circuit board having a three-layer dielectric body and four-layer ground layer structure, according to the present invention, comprises: a first dielectric body; a second dielectric body facing the flat surface of the first dielectric body; a third dielectric body facing the bottom side of the first dielectric body; a signal line formed on the flat surface of the first dielectric body; a pair of first ground layers laminated on the flat surface of the first dielectric body and having the signal line therebetween; second ground layers laminated on the bottom side of the first dielectric body so as to correspond to the first ground layers; a third ground layer laminated on the flat surface of the second dielectric body; and a fourth ground layer laminated on the bottom side of the third dielectric body.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 23, 2019
    Assignee: GIGALANE CO., LTD.
    Inventors: Sang Pil Kim, Da Yeon Lee, Hwang Sub Koo, Hyun Je Kim, Hee Seok Jung
  • Patent number: 10362676
    Abstract: Provided is a substrate including a first wiring layer coupled to another wiring layer through a plurality of vias, wherein in the first wiring layer, an area of a first region except an aperture is greater than an area of a second region except an aperture, the first region being enclosed by a first line segment passing through a first connection part of a first via and being parallel to a first short side of the first wiring layer and a second line segment passing through a second connection part of a second via and being parallel to the first short side, the second region being enclosed by the second line segment and a third line segment passing through a third connection part of a third via and being parallel to the first short side, the first, second, and third connection parts connecting to the first wiring layer.
    Type: Grant
    Filed: January 8, 2019
    Date of Patent: July 23, 2019
    Assignee: FUJITSU LIMITED
    Inventor: Shinichi Nakamoto
  • Patent number: 10349533
    Abstract: A multilayer circuit board comprises an inner circuit board, a tin layer, at least one outer circuit board, and a solder mask. The inner circuit board comprises at least one first mounting region and at least one second mounting region. The tin layer is formed on a surface of the inner circuit board except the first mounting region connecting the outer circuit board. The outer circuit board comprises at least one first opening to expose the first mounting region and at least one second opening to expose a portion of the tin layer covering the second mounting region. The inner circuit board, the tin layer, and the outer circuit board together form a middle structure. The solder mask covers the middle structure except the portion and the first mounting region. A treatment layer is formed on the first mounting region.
    Type: Grant
    Filed: December 29, 2018
    Date of Patent: July 9, 2019
    Assignees: HongQiSheng Precision Electronics (QinHuangDao) Co., Ltd., Avary Holding (Shenzhen) Co., Limited.
    Inventors: Li-Kun Liu, Yan-Lu Li
  • Patent number: 10347553
    Abstract: Each of a plurality of ceramic substrate members includes a via reaching an other main surface from one main surface. A gap is formed in each of first and second ceramic substrate members of the plurality of stacked ceramic substrate members to penetrate each of the first and second ceramic substrate members, the first ceramic substrate member being arranged at an outermost surface on one side in a stacking direction of the ceramic substrate members, the second ceramic substrate member being arranged at an outermost surface on the other side opposite to the one side in the stacking direction. At least a portion of a side surface and a bottom surface within the gap are covered with a protection layer. The protection layer is made of a material having an etching rate lower than that of the ceramic substrate members.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: July 9, 2019
    Assignee: Mitsubishi Electric Corporation
    Inventors: Nobuaki Konno, Yoshiaki Hirata, Yukihisa Yoshida
  • Patent number: 10349517
    Abstract: In one implementation, a printed circuit board (PCB) includes a plurality of pads that form a pad pattern on the PCB. In that implementation, the plurality of pads include a group of load pads, a dummy pad, and a false pad. The group of load pads act as contact points to establish an electrical path between a first circuitry and a second circuitry. The dummy pad is coupled to a via that floats electrically and the false pad is coupled to a third circuitry.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: July 9, 2019
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Charles Nathan Logan, Adrian Rothenbuhler, Christine M. Wells
  • Patent number: 10342143
    Abstract: A production method includes: preparing a metal clad laminate including a dielectric layer?30 ?m thick, a first metal foil on a first surface of the dielectric layer, a second metal foil on a second surface of the dielectric layer, first and second carriers on the metal foil via a releasable layer; arranging the pair of metal clad laminates on a resin substrate so the first carrier of each metal clad laminate faces the resin substrate on each surface of the resin substrate; releasing the second carrier from a laminated member to expose the second metal foil; forming a pattern on the second metal foil; arranging an insulating layer on the pattern and arranging a metal layer on the insulating layer; and separating the first carrier and the first metal foil from each other. The dielectric layer has a strain energy at break of 1.8 MJ or less.
    Type: Grant
    Filed: November 18, 2016
    Date of Patent: July 2, 2019
    Assignee: MITSUI MINNG & SMELTING CO., LTD.
    Inventors: Toshiyuki Shimizu, Toshifumi Matsushima, Yoshihiro Yoneda
  • Patent number: 10334740
    Abstract: An electronic-component mount substrate includes a substrate having a first principal surface and a second principal surface opposite to the first principal surface; a mount electrode for mounting an electronic component on the first principal surface, the mount electrode having a first slit and sandwiching the first slit; a plane electrode surrounding the mount electrode in a plan view and having a second slit; a connection electrode connecting the mount electrode with the plane electrode; and an outer electrode on the second principal surface. The connection electrode overlaps the outer electrode and an outer edge of the outer electrode surrounds the connection electrode in a perspective plan view.
    Type: Grant
    Filed: August 29, 2017
    Date of Patent: June 25, 2019
    Assignee: Kyocera Corporation
    Inventor: Kensaku Murakami
  • Patent number: 10332824
    Abstract: A lead frame includes: a plurality of units each including a first lead portion and a second lead portion arranged in a first direction, wherein the units are arranged in the first direction and in a second direction perpendicular to the first direction, and the first lead portion and the second lead portion of each unit are adjacent, in the second direction, to the first lead portion and the second lead portion of an adjacent one of the units that is adjacent in the second direction; a plurality of first suspension portions; and a plurality of connecting portions. Each of the first suspension portions connects, in the second direction, the first lead portions of units that are adjacent to each other in the second direction.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: June 25, 2019
    Assignee: NICHIA CORPORATION
    Inventors: Hironao Oku, Toshiyuki Hashimoto, Mitsuhiro Isono, Takao Ishihara, Takaaki Kato
  • Patent number: 10327325
    Abstract: A printed circuit board (1) comprising an insulating layer (2) and a conducting layer (3) arranged on the insulating layer (2) and structured into a contact surface (4) for an electronic component (11) which is to be populated on the printed circuit board (1) has, in the area of the contact surface (4), at least one channel (8) that passes through the contact surface (4) and the insulating layer (2) and that is filled with a thermally conductive material.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: June 18, 2019
    Assignee: ZK W Group GmbH
    Inventors: Erik Edlinger, Dietmar Kieslinger
  • Patent number: 10321573
    Abstract: Embodiments of the present disclosure are directed towards techniques and configurations to provide solder contacts for electrical connection in socket assemblies. In one embodiment, a solder contact may be disposed on the bottom surface of a die package such that the solder contact is conductively coupled to electrical contacts of the die package. The solder contacts may be disposed to be coupled to pins of a socket assembly, to provide conductive coupling of the electrical contacts of the die package and the pins of the socket assembly. The solder may be selected to be sufficiently soft to provide for better electrical conduction. The pins may also be configured to penetrate the solder contact to provide for better electrical conduction. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 11, 2019
    Assignee: INTEL CORPORATION
    Inventors: Fay Hua, Hong Xie, Gregorio R. Murtagian, Amit Abraham, Alan C. McAllister, Ting Zhong
  • Patent number: 10321582
    Abstract: A method of manufacturing a wiring board includes a stacking process in which N (N is an integer equal to or greater than 2) wiring layers, end portions of which include linear conductor patterns, are stacked, with the end portions superimposed, via substrates (insulating layers) provided among the wiring layers and a laminated plate is manufactured and a removing process in which the insulating layers around the end portions of the conductor patterns of the laminated plate are removed to machine the end portions into N flying leads projecting from an end face.
    Type: Grant
    Filed: July 18, 2017
    Date of Patent: June 11, 2019
    Assignee: OLYMPUS CORPORATION
    Inventor: Jumpei Yoneyama
  • Patent number: 10308786
    Abstract: Provided are a power inductor including a body, a base disposed in the body, a coil disposed on the base, a first external electrode connected to the coil, the first external electrode being disposed on a side surface of the body, and a second external electrode connected to the first external electrode, the second external electrode being disposed on a bottom surface of the body and a method for manufacturing the same.
    Type: Grant
    Filed: April 27, 2015
    Date of Patent: June 4, 2019
    Assignee: MODA-INNOCHIPS CO., LTD.
    Inventors: In Kil Park, Gyeong Tae Kim, Seung Hun Cho, Jun Ho Jung, Ki Joung Nam, Jung Gyu Lee
  • Patent number: 10314162
    Abstract: Apparatuses and associated methods are described that provide networking connections that reduce cross-talk and other interference in communications systems. The network connection includes a printed circuit board (PCB) that defines a first end, a second end, and a grounding region on a surface of the PCB proximate the first end. The network connection includes network connectors proximate the first end, soldering pad pairs proximate the second end, and electrical traces therebetween. At least a first soldering pad pair is offset from a second soldering pad pair with respect to an edge of the PCB at the second end, such that, in an operational configuration in which at least the first soldering pad pair and the second soldering pad pair receive a differential signal cable, each differential signal cable is supported by the PCB in a corresponding offset configuration thereby reducing cross-talk between the differential signal cables.
    Type: Grant
    Filed: July 13, 2018
    Date of Patent: June 4, 2019
    Assignee: MELLANOX TECHNOLOGIES, LTD.
    Inventors: Dor Oz, Uri Goffer-Dor, Boris Sharav
  • Patent number: 10312187
    Abstract: A multi-row wiring member for semiconductor device configured of a plurality of wiring members arrayed in a matrix includes a resin layer, a first plating layer forming internal terminals, a plating layer forming wiring portions and a second plating layer forming external terminals. The first plating layer is formed in the resin layer with lower faces thereof uncovered in the bottom surface of the resin layer. The plating layer forming wiring portions is formed on the first plating layer in the resin layer. The second plating layer is formed on partial areas within areas of the plating layer forming wiring portions, with upper faces thereof being uncovered on a top-surface side of the resin layer. On a bottom-surface side of the resin layer, a resin frame is integrally formed with the resin layer at the margin around an aggregate of individual wiring members for semiconductor devices arrayed in a matrix.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: June 4, 2019
    Assignee: Ohkuchi Materials Co., Ltd.
    Inventors: Kaoru Hishiki, Ichinori Iidani
  • Patent number: 10306774
    Abstract: A laminate structure of metal coating is laminated on a base material, and includes a primer layer, a catalyst layer and a plating deposited layer. The primer layer is a resin layer with a glass transition temperature (Tg) of 40 to 430° C. The catalyst layer is a metal nanoparticle group arranged in a plane on the primer layer, wherein the metal nanoparticle group is a metal in Group 11 or Groups 8, 9 and 10 in a periodic table, and the metal nanoparticles are surrounded by the primer layer. Ends of the metal nanoparticles are attached to the plating deposited layer.
    Type: Grant
    Filed: September 13, 2017
    Date of Patent: May 28, 2019
    Assignee: ELECTROPLATING ENGINEERS OF JAPAN LIMITED.
    Inventor: Masahiro Ito
  • Patent number: 10306756
    Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: May 28, 2019
    Assignee: Sierra Circuits, Inc.
    Inventors: Kenneth S. Bahl, Konstantine Karavakis