Patents Examined by Jeremy C. Norris
  • Patent number: 10842018
    Abstract: An interlayer transmission line includes a plurality of dielectric layers stacked on each other, a signal via that penetrates the plurality of dielectric layers in a stacking direction, and mutually connects signal patterns disposed on two external faces of the plurality of dielectric layers externally exposed, a ground plane that is disposed between the dielectric layers, and covers an area surrounding a circular removal region centered around the signal via, and a plurality of ground vias that penetrate at least one layer of the dielectric layers in the stacking direction of the dielectric layers, are disposed along a plurality of concentric circles centered around the signal via, and are electrically connected with the ground plane.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: November 17, 2020
    Assignee: DENSO CORPORATION
    Inventors: Kazumasa Sakurai, Kazuya Wakita
  • Patent number: 10834819
    Abstract: A printed circuit board includes an electronic component having a first land, and a printed wiring board having a second land soldered to the first land. The printed wiring board includes a first wiring pattern, a resist opening formed around the second land configured to expose at least part of the first wiring pattern to outside, and a second wiring pattern disposed at least a portion of a periphery of the resist opening. A heat capacity of the first wiring pattern is smaller than that of the second wiring pattern.
    Type: Grant
    Filed: October 14, 2019
    Date of Patent: November 10, 2020
    Assignee: CANON KABUSHIKI KAISHA
    Inventor: Dai Naito
  • Patent number: 10834856
    Abstract: An electronic control unit has a substrate that includes a terminal connection portion that is a through hole that extends through the substrate from a first surface to a second surface. A resist opening along an outer edge of the terminal connection portion exposes a circuit pattern from a surface resist layer. A plurality of vias are disposed at positions adjacent to the resist opening in a heat receiving area to facilitate the transfer of heat during a soldering process from the first surface to the second surface.
    Type: Grant
    Filed: July 18, 2019
    Date of Patent: November 10, 2020
    Assignee: DENSO CORPORATION
    Inventor: Hiroyasu Sugiura
  • Patent number: 10827605
    Abstract: The present disclosure relates to a 5th generation (5G) or pre-5G communication system for supporting a higher data transmission rate than 4th generation (4G) communication systems such as long term evolution (LTE).
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: November 3, 2020
    Assignee: Samsung Electronic Co., Ltd.
    Inventors: Man-Ho Kim, Jong-Wan Shim, Hwa Joong Jung, Tae-Yun Kim, Yonghwan Choi, Kihuk Lee
  • Patent number: 10820412
    Abstract: A circuit wire crossing structure, comprising a substrate with a supporting surface, an electrical circuit disposed on the supporting surface of the substrate, with the electrical circuit comprising, two lateral wires with one of the wires having a first terminal and a second terminal and another one of the lateral wires having a second terminal, wherein the first terminal and the second terminal are spaced apart from each other, and a central wire, disposed between and apart from the first terminal and the second terminal, and an electronic component arranged above the supporting surface and two terminals of the electronic component connecting with the first terminal and the second terminal, wherein the electronic component has an insulating shell facing the central wire, and an orthographic projection of the electronic component to the supporting surface extends across an orthographic projection of the central wire to the supporting surface.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: October 27, 2020
    Assignee: CYMMETRIK ENTERPRISE CO., LTD.
    Inventors: Shan-Jen Kuo, Frank Shang-Teng Chan, Yosephine Yulia Margaretha, Jung-Da Cheng, Jen-Chieh Wei
  • Patent number: 10818586
    Abstract: A substrate structure is provided. The substrate structure includes a substrate, a first redistribution structure, a first adhesive layer and a first connecting component. The substrate includes a first conductor on a first surface thereof. The first redistribution structure is disposed over the substrate. The first adhesive layer is disposed between the substrate and the first redistribution structure. The first connecting component is electrically connected with the first conductor, penetrates through the first adhesive layer into the first redistribution structure, and electrically connects the substrate to the first redistribution structure.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: October 27, 2020
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventor: Wen-Long Lu
  • Patent number: 10813221
    Abstract: A mounted board includes a base insulating layer, a conductive pattern, and a cover insulating layer sequentially toward one side in a thickness direction. The entire lower surface of the base insulating layer is exposed downwardly. A total thickness of the base insulating layer and the cover insulating layer is 16 ?m or less. The base insulating layer contains an insulating material having a hygroscopic expansion coefficient of 15×10?6/% RH or less.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: October 20, 2020
    Assignee: NITTO DENKO CORPORATION
    Inventors: Shusaku Shibata, Hayato Takakura, Yoshihiro Kawamura, Shuichi Wakaki
  • Patent number: 10813228
    Abstract: Implementations of the disclosure describe techniques for eliminating or reducing hot tearing in via-in-pad plated over (VIPPO) solder joints by incorporating an adhesive into a printed circuit board assembly (PCBA). In an embodiment, the adhesive is an adhesive containing fluxing agent that prevents tearing by reducing a differential in thermal expansion caused by a coefficient of thermal expansion (CTE) mismatch between a plated metal of the VIPPO pads and the PCB substrate.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: October 20, 2020
    Assignee: INDIUM CORPORATION
    Inventors: Lee C. Kresge, Elaina J. Zito, Ning-Cheng Lee
  • Patent number: 10813218
    Abstract: A resin multilayer board includes a substrate including a stack of resin layers, and a first metal pin including a first end portion exposed at a first main surface of the substrate and penetrating through at least one of the resin layers in a thickness direction, wherein a gap is provided at a portion of an interface between a lateral side of the first metal pin and the resin layer.
    Type: Grant
    Filed: February 12, 2020
    Date of Patent: October 20, 2020
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Atsushi Kasuya, Yusuke Kamitsubo
  • Patent number: 10806031
    Abstract: There is provided an organic insulating body which contains a cyclic olefin copolymer as a main component and a peroxide having a benzene ring, and has such a property that a loss tangent peak appears at 120° C. or higher in a dynamic mechanical analysis.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: October 13, 2020
    Assignee: KYOCERA CORPORATION
    Inventors: Tadashi Nagasawa, Chie Chikara, Satoshi Kajita
  • Patent number: 10806029
    Abstract: A catalytic resin is formed by mixing a resin and either homogeneous or heterogeneous catalytic particles, the resin infused into a woven glass fabric to form an A-stage pre-preg, the A-stage pre-preg cured into a B-stage pre-preg, thereafter held in a vacuum and between pressure plates at a gel point temperature for a duration of time sufficient for the catalytic particles to migrate away from the resin rich surfaces of the pre-preg, thereby forming a C-stage pre-preg after cooling. The C-stage pre-preg subsequently has trenches formed by removing the resin rich surface, the trenches extending into the depth of the catalytic particles, optionally including drilled holes to form vias, and the C-stage pre-preg with trenches and holes placed in an electroless bath, whereby traces form in the trenches and holes where the surface of the cured pre-preg has been removed.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: October 13, 2020
    Assignee: CATLAM, LLC
    Inventors: Kenneth S. Bahl, Konstantine Karavakis
  • Patent number: 10804621
    Abstract: According to one embodiment, a printed wiring board includes a wiring board, a connector part, a connection pad provided between the wiring board and the connector part and connected with the connector part with a solder material and a guide groove provided in the wiring board to be continuous to the connection pad, to guide a portion of the solder material from the connection pad.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: October 13, 2020
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Akira Tanaka, Masaya Hirashima, Satoru Yasui, Shukuyo Yamada, Masashi Watanabe
  • Patent number: 10806028
    Abstract: Provided is a method for manufacturing a metal-layer-joined ceramic base material board, in which at least one scribe line is formed, on each of the front and back surfaces of a ceramic base material board, along dividing lines for dividing the ceramic base material board into a plurality of ceramic boards, a metal board covering at least a portion of the dividing lines is joined to each of the front and back surface of the ceramic base material board, the metal boards are etched along the dividing lines to form a plurality of metal layers, and the plurality of metal layers are joined to each of the front and back surfaces of the ceramic base material board.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 13, 2020
    Assignee: MITSUBISHI MATERIALS CORPORATION
    Inventors: Koya Arai, Masahito Komasaki
  • Patent number: 10798828
    Abstract: A method of fabricating a circuit board structure is provided. The method includes providing a core substrate; forming an insulation layer on the core substrate; forming a patterned metal layer on the insulation layer, wherein the patterned metal layer includes a wiring layer and a pad; forming a first metal pillar on the pad, wherein the first metal pillar has a top surface; and forming a first solder resist layer on the patterned metal layer and the first metal pillar, wherein the first solder resist layer has a first opening exposing the first metal pillar, and the first opening has a bottom surface, wherein the top surface of the metal pillar is higher than or equal to the bottom surface of the first opening.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: October 6, 2020
    Assignee: NAN YA PRINTED CIRCUIT BORED CORPORATION
    Inventor: Hsien-Chieh Lin
  • Patent number: 10798827
    Abstract: A printed circuit board includes an insulating layer, a circuit pattern on the insulating layer, and a surface treatment layer on the circuit pattern. The surface treatment layer includes a bottom surface having a width wider than a width of a top surface of the circuit pattern.
    Type: Grant
    Filed: December 17, 2019
    Date of Patent: October 6, 2020
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Yun Mi Bae, Soon Gyu Kwon, Sang Hwa Kim, Sang Young Lee, Jin Hak Lee, Han Su Lee, Dong Hun Jeong, In Ho Jeong, Dae Young Choi, Jung Ho Hwang
  • Patent number: 10791633
    Abstract: A thick conductor built-in type printed wiring board includes a printed wiring board, an insulating resin layer, an insulating base material layer, and a conductor layer. The printed wiring board includes an insulating layer including a cured product of a first resin composition, and a circuit provided on one main surface or both main surfaces of the insulating layer, the circuit having a plurality of conductor wirings each having a thickness ranging from 105 ?m to 630 ?m, inclusive. The insulating resin layer covers a surface of the printed wiring board on which the circuit is provided, and includes a cured product of a second resin composition and includes no fibrous base material. The insulating base material layer covers the insulating resin layer, and includes a cured product of a third resin composition and a fibrous base material. The conductor layer covers the insulating base material layer.
    Type: Grant
    Filed: December 18, 2017
    Date of Patent: September 29, 2020
    Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
    Inventors: Akira Ito, Eiichiro Saito, Naohito Fukuya
  • Patent number: 10791630
    Abstract: A printed circuit board having conductor tracks formed on one side of a substrate. The substrate is able to be cohesively bonded at a contact face to a cover for protecting the conductor tracks. In this case, the substrate includes a step, which forms a barrier with respect to an auxiliary material for promoting the cohesive bond, in order to prevent any wetting of the conductor tracks with the auxiliary material. A sensor having a printed circuit board for use in a fuel filling level measurement system of a vehicle.
    Type: Grant
    Filed: July 12, 2017
    Date of Patent: September 29, 2020
    Assignee: Vitesco Technologies GmbH
    Inventors: Erich Mattmann, Robert Peter, Waldemar Brinkis, Martin Maasz, Burkhard Dasbach
  • Patent number: 10791632
    Abstract: A board element for board-to-board interconnect formation is provided. An embodiment includes embedding a signal via element in the board element and cutting through respective sections of the board element and the signal via element to expose a new board element edge and an outwardly facing surface of the signal via element.
    Type: Grant
    Filed: September 20, 2019
    Date of Patent: September 29, 2020
    Assignee: RAYTHEON COMPANY
    Inventors: Chad E. Patterson, Michael M. Fitzgibbon
  • Patent number: 10791629
    Abstract: An electronic device includes a printed circuit board (PCB). The PCB includes first and second grids disposed at a top surface and a bottom surface of the PCB, respectively. Each grid includes a plurality of footprint pins, and a plurality of vias extending through the PCB to the top and bottom surfaces. Each footprint pin includes a connecting end and a free end that opposes the connecting end. Each via includes a contact end located at one of grids and is in electrical contact with the connecting end of one of the footprint pins, and each via further includes a non-contact end that is located at the other of the grids and is not in electrical contact with any of the footprint pins. First and second connectors are mounted to the PCB top and bottom surfaces and connect with the footprint pins of the first and second grids.
    Type: Grant
    Filed: November 13, 2019
    Date of Patent: September 29, 2020
    Assignee: CISCO TECHNOLOGY, INC.
    Inventors: Fanghui Ren, Liang Xue
  • Patent number: 10774231
    Abstract: An object of the present invention is to provide a composition for sintering capable of suppressing a crack from occurring in a wiring after sintering. Provided is the composition for sintering including silver nanoparticles, an organic dispersant for coating the silver nanoparticles, and a solvent. When the composition for sintering is heated, a weight loss rate in a range of 260° C. to 600° C. is 2.92% or less.
    Type: Grant
    Filed: July 2, 2019
    Date of Patent: September 15, 2020
    Assignee: STANLEY ELECTRIC CO., LTD.
    Inventors: Hiroto Fukushima, Akihiko Hanya