Abstract: A semiconductor structure and method for forming same are provided. The forming method includes: providing a base; forming a discrete core layer on the base; forming a spacer on a sidewall of the core layer; removing the core layer; after the core layer is removed, patterning the base using the spacer as a mask to form a fin, the fin including a device fin and a dummy fin; removing the spacer; performing doping removal on the dummy fin one or more times to remove the dummy fin, the step of the doping removal including: performing ion doping on the entire dummy fin or a part of the dummy fin in thickness for improving an etching selection ratio of the dummy fin to the device fin; and removing the ion-doped dummy fin. Embodiments and implementations of the present disclosure help increase a process window of a fin cut process.

Abstract: A display apparatus includes a substrate including a display area including a main display area and an edge display area extended directly from a side of the main display area, and a peripheral area outside the display area and including a pad area through which electrical signals are applied to the display area; and in the peripheral area, a plurality of wirings between the display area and the pad area and through which the electrical signals are transmitted from the pad area to the display area, the plurality of wirings including: a first wiring through which an electrical signal is transmitted from the pad area to the main display area, and a second wiring through which an electrical signal is transmitted from the pad area to the edge display area, where an electrical resistance per unit length of the first wiring is greater than that of the second wiring.

Abstract: A method for manufacturing a semiconductor device includes forming a plurality of gate structures on a semiconductor fin, and forming a plurality of source/drain regions adjacent the plurality of gate structures. In the method, a germanium oxide layer is formed on the plurality of gate structures and on the plurality of source/drain regions, and portions of the germanium oxide layer on the plurality of source/drain regions are converted into a plurality of dielectric layers. The method also includes removing unconverted portions of the germanium oxide layer from the plurality of gate structures, and depositing a plurality of cap layers in place of the removed unconverted portions of the germanium oxide layer. The plurality of dielectric layers are removed, and a plurality of source/drain contacts are formed on the plurality of source/drain regions. The plurality of source/drain contacts are adjacent the plurality of cap layers.

Abstract: An integrated circuit (IC) structure with a single active region having a doping profile different than that of a set of active regions, is disclosed. The IC structure provides a single active region, e.g., a fin, on a substrate with a first doping profile, and a set of active regions, e.g., fins, electrically isolated from the single active region on the substrate. The set of active regions have a second doping profile that is different than the first doping profile of the single active region. For example, the second doping profile can have a deeper penetration into the substrate than the first doping profile.

Abstract: In some examples, a semiconductor device, comprises a semiconductor substrate; an epitaxial layer having a top side disposed on the semiconductor substrate, wherein the epitaxial layer has a source implant region, a drain implant region, a first doped region, and a second doped region, wherein the first doped region is adjacent to the source implant region and the second doped region is adjacent to the drain implant region, wherein the top side has a sloped surface over the second doped region; a gate electrode supported by the top side; a source electrode in contact with the source implant region; and a drain electrode in contact with the drain implant region.

Abstract: An organic light emitting diode display device includes a substrate, a light emitting layer, a first power supply wire, a second power supply wire, a connection pattern, and an upper electrode. The substrate has a display region, a peripheral region surrounding the display region and including first, second, and third peripheral regions, and a pad region disposed on one side of the peripheral region. The light emitting layer is disposed in the display region on the substrate. The first power supply wire is disposed in the second and third peripheral regions and a part of the first peripheral region on the substrate. The second power supply wire is disposed in the display region, the first peripheral region, and the third peripheral region on the substrate without being disposed in the second peripheral region, and is located inward of the first power supply wire.

Abstract: A semiconductor device includes a substrate including an active region extending in a first direction; a gate structure intersecting the active region and extending in a second direction on the substrate, the gate structure including a gate electrode, a gate capping layer on the gate electrode, and a plurality of spacers on side surfaces of the gate electrode; source/drain regions on the active region on at least one side of the gate structure; a first insulating layer and a second insulating layer on the source/drain regions on at least one side of the gate structure; and contact plugs on the source/drain regions and penetrating the first and second insulating layers.

Abstract: Integrated circuit transistor structures and processes are disclosed that reduce n-type dopant diffusion, such as phosphorous or arsenic, from the source region and the drain region of a germanium n-MOS device into adjacent channel regions during fabrication. The n-MOS transistor device may include at least 70% germanium (Ge) by atomic percentage. In an example embodiment, source and drain regions of the transistor are formed using a low temperature, non-selective deposition process of n-type doped material. In some embodiments, the low temperature deposition process is performed in the range of 450 to 600 degrees C. The resulting structure includes a layer of doped mono-crystyalline silicon (Si), or silicon germanium (SiGe), on the source/drain regions. The structure also includes a layer of doped amorphous Si:P (or SiGe:P) on the surfaces of a shallow trench isolation (STI) region and the surfaces of contact trench sidewalls.

Abstract: The present disclosure proposes a thin film transistor and a related circuit. The thin film includes a gate, a drain and a source. The gate includes one or more gate units. The gate unit includes two or more strip-shaped gate branches, and a first gap is arranged between the two adjacent strip-shaped gate branches to separate them.

Abstract: There is provided a technique for suppressing the operation of a parasitic transistor in a semiconductor device having a voltage sense structure. The semiconductor device includes: a semiconductor layer; a first impurity region; a second impurity region; a first semiconductor region; a second semiconductor region; a first electrode; a second electrode; and a third electrode. The second impurity region includes a low lifetime region at least under the second semiconductor region. The low lifetime region is a region having a defect density higher than that in a surface layer of the second impurity region or a region in which a heavy metal is diffused.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device is disclosed. The method of manufacturing a semiconductor device, includes forming an organic film containing polyacrylonitrile on a target film on a semiconductor substrate; applying a metal compound to the organic film to form a composite film; removing the composite film partially to form a pattern; heating the pattern-formed composite film; and processing the target film by using the heated composite film as a mask.

Abstract: A semiconductor device includes a first fin structure disposed on a substrate. The first fin structure extends in a first direction. A first sacrificial layer pattern is disposed on the first fin structure. The first sacrificial layer pattern includes a left portion and a right portion arranged in the first direction. A dielectric layer pattern is disposed on the first fin structure and interposed between the left and right portions of the first sacrificial layer pattern. A first active layer pattern extending in the first direction is disposed on the first sacrificial layer pattern and the dielectric layer pattern. A first gate electrode structure is disposed on a portion of the first active layer pattern. The portion of the first active layer is disposed on the dielectric layer pattern. The first gate electrode structure extends in a second direction crossing the first direction.

Abstract: A semiconductor wafer has an edge support ring around a perimeter of the semiconductor wafer and conductive layer formed over a surface of the semiconductor wafer within the edge support ring. A first stencil is disposed over the edge support ring with first openings aligned with the conductive layer. The first stencil includes a horizontal portion over the edge support ring, and a step-down portion extending the first openings to the conductive layer formed over the surface of the semiconductor wafer. The horizontal portion may have a notch with the edge support ring disposed within the notch. A plurality of bumps is dispersed over the first stencil to occupy the first openings over the conductive layer. A second stencil is disposed over the edge support ring with second openings aligned with the conductive layer to deposit a flux material in the second openings over the conductive layer.

Abstract: The present disclosure relates to a display substrate, a method of manufacturing the same, and a display substrate. The display substrate includes: a light-emitting portion located in a display region of the display substrate; one or more dams located in a non-display region of the display substrate, the non-display region surrounding the display region; a first stress absorbing portion arranged below at least one dam of the dams.

Abstract: A transistor includes a semiconductor fin with a subfin layer of a subfin material selected from a first group III-V compound a channel layer of a channel material directly on the subfin layer and extending upwardly therefrom, the channel material being a second group III-V compound different from the first group III-V compound. A gate structure is in direct contact with the channel layer of the semiconductor fin, where the gate structure is further in direct contact with one of (i) a top surface of the subfin layer, the top surface being exposed where the channel layer meets the subfin layer because the channel layer is narrower than the subfin layer, or (ii) a liner layer of liner material in direct contact with opposing sidewalls of the subfin layer, the liner material being distinct from the first and second group III-V compounds.

Abstract: A display device including TFTs in a pixel area and in a peripheral driving area in which the number of through-holes in a TFT circuit is decreased, and the mounting density of the TFTs is improved, so that a high-resolution display can be achieved. The display device includes a display area in which pixels are disposed in a matrix form, and a TFT substrate, on which a peripheral driving circuit is disposed, on the outer side of the display area. The pixels or the peripheral driving circuit includes TFTs (thin film transistors) each of which is formed in such a way that a first gate electrode of each TFT is formed relative to a semiconductor layer with a first gate insulating film therebetween, and a drain electrode and a source electrode of each TFT that are connected to the semiconductor layer are formed at layers different from each other.

Abstract: A silicon chip carrier includes at least two of a photosensitive P-I-N diode, a non-photosensitive P-I-N diode, a photosensitive P-(metal)-N diode, a non-photosensitive P-(metal)-N diode, and a Schottky diode all integrally formed in the same layers of the chip carrier. In some embodiments, diodes formed in the chip carrier provide photovoltaic power and power regulation to a circuit mounted on the chip carrier.

Abstract: A technique relates to a semiconductor device. A source/drain layer is formed. Fins with gate stacks are formed in a fill material, a dummy fin template including at least one fin of the fins and at least one gate stack of the gate stacks, the fins being formed on the source/drain layer. A trench is formed through the fill material by removing the dummy fin template, such that a portion of the source/drain layer is exposed in the trench. A source/drain metal contact is formed on the portion of the source/drain layer in the trench.

Abstract: FETs including a gated oxide semiconductor spacer interfacing with a channel semiconductor. Transistors may incorporate a non-oxide channel semiconductor, and one or more oxide semiconductors disposed proximal to the transistor gate electrode and the source/drain semiconductor, or source/drain contact metal. In advantageous embodiments, the oxide semiconductor is to be gated by a voltage applied to the gate electrode (i.e., gate voltage) so as to switch the oxide semiconductor between insulating and semiconducting states in conjunction with gating the transistor's non-oxide channel semiconductor between on and off states.

Abstract: A display panel and a display device are provided. The display panel has an array substrate, a planarization layer, an anode layer, a light emitting device layer having light emitting device units, a plurality of pixel defining bodies, and a plurality of blocking walls disposed between the neighboring light emitting device units for blocking water and oxygen. Each of the blocking walls contacts with at least one of the planarization layer and the anode layer, and an upper surface of one of the blocking walls is not lower than an upper surface of one of the pixel defining bodies.