Abstract: A high power vertical insulated-gate switch is described that includes a parallel cell array having inner cells and an edge cell. The cells have a vertical npnp structure with a trenched field effect device that turns the device on and off. The edge cell is prone to breaking down at high currents. Techniques used to cause the current in the edge cell to be lower than the current in the inner cells, to improve robustness, include: forming a top n-type source region to not extend completely across opposing trenches in areas of the edge cell; forming the edge cell to have a threshold voltage of its field effect device that is greater than the threshold voltage of the field effect devices in the inner cells; and providing a resistive layer between the edge cell and a top cathode electrode electrically contacting the inner cells and the edge cell.

Abstract: A semiconductor device having a gate-all-around structure includes a first fin pattern and a second fin pattern separated by a first trench and extending in a first direction, a first nanosheet on the first fin pattern, a second nanosheet on the second fin pattern, a first fin liner extending along at least a portion of a sidewall and a bottom surface of the first trench, a first field insulation layer disposed on the first fin liner and filling a portion of the first trench, and a first gate structure overlapping an end portion of the first fin pattern and including a first gate spacer. A height from the bottom surface of the first trench to a lower surface of the first gate spacer is greater than a height from the bottom surface of the first trench to an upper surface of the first field insulation layer.

Abstract: According to one embodiment, a semiconductor device includes a semiconductor layer, a charge storage layer provided on the surface of the semiconductor layer via a first insulating film, and an electrode layer provided on the surface of the charge storage layer via a second insulating film. The first insulating film includes a first region where the compositional ratio of nitrogen to silicon, oxygen and nitrogen varies from a first value to a second value, which is lower than the first value, along a first direction from the semiconductor layer toward the charge storage layer.

Abstract: A method includes providing a single crystal substrate having a buffer layer on a surface of the substrate. The buffer layer provides a transition between the crystallographic lattice structure of the substrate and the crystallographic lattice structure of the semiconductor layer and has its resistivity increased by ion implanting a dopant into the buffer layer; and forming semiconductor layer on the ion implanted buffer layer. The semiconductor layer may be a wide bandgap semiconductor layer having a high electron mobility transistors formed therein.

Abstract: Embodiments are disclosed for processing microelectronic workpieces having patterned structures to improve mandrel pull from spacers for multi-color patterning. The disclosed embodiments form patterned structures on a substrate including mandrels, form spacers adjacent the mandrels that are recessed such that a height of the spacers is less than the height of the mandrels, form protective caps over the spacers while exposing top surfaces of the mandrels, and remove the mandrels to leave a spacer pattern with cap protection. The remaining spacer pattern can then be transferred to underlying layers in additional process steps. The recessing of the spacers and formation of the protective caps tends to reduce or eliminate spacer damage suffered by prior solutions during mandrel pull from spacers for multi-color patterning.

Abstract: A manufacturing method of semiconductor device includes providing a substrate, forming a sacrificial layer on the substrate, disposing first chips on the sacrificial layer, forming a first dielectric layer surrounding the first chips, forming trenches in the first dielectric layer, and forming a second dielectric layer in the trenches, wherein an upper surface of the first dielectric layer and an upper surface of the second dielectric layer are at a same plane.

Abstract: Disclosed is a display device including: a substrate; a first insulating film over the substrate, the first insulating film exposing a part of the substrate to provide an exposed surface to the substrate; a second insulating film in contact with the exposed surface and a first side surface of the first insulating film; and a first wiring over the second insulating film and in contact with the exposed surface, the first insulating film, and the second insulating film. The display device may further possess a third insulating film spaced from the second insulating film and in contact with the exposed surface. The first insulating film has a second side surface opposing the first side surface through the exposed surface. The third insulating film may be in contact with the second side surface, and the wiring may be located over and in contact with the third insulating film.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.

Abstract: An LDMOS device includes a doped drift region of a first conductivity type formed on an upper surface of a substrate having a second conductivity type. A body region of the second conductivity type is formed proximate an upper surface of the doped drift region. Source and drain regions of the first conductivity type are formed proximate an upper surface of the body region and doped drift region, respectively, and spaced laterally from one another. A gate is formed over the body region and between the source and drain regions. The gate is formed on a first insulating layer for electrically isolating the gate from the body region. A shielding structure is formed over at least a portion of the doped drift region on a second insulating layer. The gate and shielding structure are spaced laterally from one another to thereby reduce parasitic gate-to-drain capacitance.

Abstract: A method of manufacturing an organic electroluminescence display panel including: preparing a substrate; forming pixel electrodes arranged in a matrix above the substrate; forming parallel column banks above the substrate in spaces between the pixel electrodes in a row direction; forming functional layers including organic light emitting layers in gaps between the column banks, including causing relative motion in the row direction between the substrate and a head provided with nozzles arranged along a column direction while ejecting ink from selected nozzles among the nozzles to supply a set of the gaps with an ink including an organic material; and forming a counter electrode above the functional layers. Among the set of the gaps, nozzle patterns of the selected nozzles for a gap differ between a first gap and a second gap in a sequence in the row direction of the set.

Abstract: An integrated circuit structure includes: a top semiconductor fin extending in a length direction; a bottom semiconductor fin extending in the length direction, the bottom semiconductor fin being under and vertically aligned with the top semiconductor fin; a top gate structure in contact with a portion of the top semiconductor fin; top source and drain regions each adjacent to the portion of the top semiconductor fin; a bottom gate structure in contact with a portion of the bottom semiconductor fin; and bottom source and drain regions each adjacent to the portion of the bottom semiconductor fin. The portion of the top semiconductor fin is between the top source region and the top drain region. The portion of the bottom semiconductor fin is between the bottom source and drain regions. Heights, widths, or both the heights and widths of the portions of the top and bottom semiconductor fins are different.

Abstract: A semiconductor structure and a forming method thereof are provided. One form of the forming method includes: providing a base, where a well region and a drift region adjacent to the well region are formed in the base; forming a trench in the drift region; forming a diffusion barrier layer in the trench; after the diffusion barrier layer is formed, forming a gate structure on the base at a junction between the well region and the drift region, where the gate structure is located on a side of the diffusion barrier layer near the well region; and forming a source region in the well region on one side of the gate structure, and forming a drain region in the drift region on the other side of the gate structure, where the drain region is located on a side of the diffusion barrier layer in the drift region away from the well region.

Abstract: To improve the joining strength between semiconductor chips. In a semiconductor device, a first semiconductor chip includes a first joining surface including a first insulating layer, a plurality of first pads to which a first inner layer circuit insulated by the first insulating layer is electrically connected, and a linear first metal layer arranged on an outside of the plurality of first pads. A second semiconductor chip includes a second joining surface joined to the first joining surface, the second joining surface including a second insulating layer, a plurality of second pads that are arranged in positions facing the first pads and to which a second inner layer circuit insulated by the second insulating layer is electrically connected, and a linear second metal layer arranged in a position facing the first metal layer.

Abstract: Integrated circuits include fins including an upper/channel region and a lower/sub-channel region, the lower region having a first chemical composition and opposing sidewalls adjacent to an insulator material, and the upper region having a second chemical composition. A first width indicates the distance between the opposing sidewalls of the lower region at a first location is at least 1 nm wider than a second width indicating the distance between the opposing sidewalls of the upper region at a second location, the first location being within 10 nm of the second location (or otherwise relatively close to one another). The first chemical composition is distinct from the second chemical composition and includes a surface chemical composition at an outer surface of the opposing sidewalls of the lower region and a bulk chemical composition therebetween, the surface chemical composition including one or more of oxygen, nitrogen, carbon, chlorine, fluorine, and sulfur.

Abstract: A display apparatus includes a light-source substrate portion which generates light; and a color control portion to which the generated light from the light-source substrate portion is incident and at which color of the generated light is adjusted to define a color-converted light having a color different from that of the generated light. The color control portion includes: an exit surface through which the color-converted light exits the color control portion; a substrate including a plurality of concave portions defined therein, each of the concave portions extended along a direction from the light-source substrate portion to the exit surface of the color control portion; and a plurality of color conversion members respectively in the plurality of concave portions, the color conversion members each including a color-converting material which converts the color of the generated light to the color of the color-converted light.

Abstract: A method is presented for forming single diffusion break (SDB) without damaging source and drain epitaxial growth regions. The method includes forming the source and drain epitaxial regions between sacrificial gates, the sacrificial gates formed over a plurality of fins, depositing an interlayer dielectric (ILD) over the source and drain epitaxial regions, performing SDB patterning, and removing at least one of the sacrificial gates to expose the plurality of fins. The method further includes recessing the plurality of fins to create a first opening, forming inner spacers within the opening, removing the plurality of fins to create a second opening, dimensions of the second opening defined by the inner spacers, and laterally etching the second opening to increase SDB width.

Abstract: A covering layer (240) is formed by atomic layer deposition (ALD) and contains an insulating inorganic material. An intermediate layer (220) contains a material having a linear expansion coefficient different from that of a material of the covering layer (240). A buffer layer (230) has a surface in contact with the intermediate layer (220), that is, a first surface. The buffer layer (230) has a surface in contact with the covering layer (240), that is, a second surface. A linear expansion coefficient difference between a material of the buffer layer (230) and the inorganic material of the covering layer (240) is less than a linear expansion coefficient difference between the material of the intermediate layer (220) and the inorganic material of the covering layer (240).

Abstract: A self-aligned multiple patterning (SAMP) process is disclosed for formation of structures on substrates. The process provides improved local critical dimension uniformity by using a first (lower) multicolor array pattern and second (upper) multicolor array pattern. The dimensions of finally formed structures are defined by the overlap of a first spacer that is formed as part of the first multicolor array pattern and a second spacer that is formed as part of the second multicolor array pattern. The spacer widths which control the critical dimension of the formed structure may be highly uniform due to the nature of spacer formation and the use of an atomic layer deposition process for forming the spacer layers of the both first (lower) multicolor array pattern and second (upper) multicolor array pattern. In one embodiment, the structure formed by a memory hole pattern for a dynamic random access memory (DRAM).

Abstract: A flexible array substrate and a display panel are provided. The flexible array substrate comprises a flexible substrate, a buffer layer, a plurality of signal lines, and pixel electrodes. The buffer layer is disposed on the flexible substrate. The plurality of signal lines is disposed on the buffer layer. A shape of the signal lines in a cross-sectional direction of the flexible array substrate is a curved shape with undulating portions or a polyline shape with undulating portions. In the disclosure, the signal line that has a curved shape with undulating portions or a polyline shape with undulating portions is disposed on the buffer layer, so that the signal line is able to cope with bending stress when bending.

Abstract: A resonant cavity-enhanced infrared photodetector has an absorber layer disposed between a first transparent layer and a second transparent layer within an optical cavity. The first transparent layer and the second transparent layer have a bandgap which is larger by at least 0.1 eV compared to the absorber layer. Since the bandgaps of the first and second layer are increased relative to the bandgap of the absorber layer, generation of dark current is limited to the absorber layer. The band profiles of the layers had been designed in order to avoid carrier trapping. In one embodiment, the conduction and valence band offsets are configured to allow unimpeded flow of photogenerated charge carriers away from the absorber layer. The photodetector may be a photoconductor, or a photodiode having n-type and p-type layers. In some embodiments, an interface between the absorber layer and a transparent layer is compositionally graded.