Abstract: A KVM switch of universal input and programmable USB hub includes a main control unit (MCU) chip and a switching control method are disclosed. The KVM switch has a MCU circuit for controlling functions of the KVM switch, complete reports of console I/O devices, reading and corresponding transmissions of descriptors; a console device interface chip connected to the MCU; a console port, connected to the console device interface chip; a computer interface chip, connected to the MCU; a re-assignment USB hub chip, connected to the computer interface chip; and a computer port, connected to the re-assignment USB hub chip. Console USB I/O interfaces become dynamic and universal, such that the console I/O devices connected to the control port correspond to the computer port to provide full compatibility, and the console ports can be connected to various console I/O devices without any limitation of device types.

Abstract: In one embodiment, a method comprises initiating shutdown of network traffic of a line card while the line card is coupled to a connector chassis and exchanging network traffic, the initiating shutdown in response to actuation of a magnetic switch associated with the line card, the magnetic switch being actuated in response to movement of actuating structure that unlocks the line card for removal from the connector chassis; and completing the shutdown of network traffic in the line card prior to permitting complete removal of the line card from the connector chassis.

Abstract: A data processing apparatus 100, to reduce power consumption for processing and wirelessly transmitting continuous data to a data reproducing apparatus 200, comprises a first signal processing unit 120 processing data stored in a data storage unit 110, a first wireless communication unit 140 wirelessly transmitting the processed data to the data reproducing apparatus, a signal processing control unit 150 controlling the first signal processing unit 120 so as to work intermittently by processing at a speed faster than real-time processing, a clock/power control unit 160 controlling supplies of clock and power to the first signal processing unit 120 and the signal processing control unit 150 during a non-operating period of the intermittent operation, and a start-up control unit 180 requesting a release of restrictions to the clock/power control unit 160 and a transfer to an operating time period of the intermittent operation to the signal processing control unit 150 based on the amount of data stored in a rece

Abstract: A power management unit for controlling power supply voltages of first and second power domains to which first and second CPUs belong respectively includes a power IC which supplies first and second power supply voltages to the first and second power domains respectively; a clock generating portion which generates first and second clocks and supplies the first and second clocks to the first and second CPUs respectively; and a power and clock control portion which is connected both to the power IC and to the clock generating portion.

Abstract: A processor-based electronic system includes several memory modules arranged in first and second ranks. The memory modules in the first rank are directly accessed by any of several processors, and the memory modules in the second rank are accessed by the processors through the memory modules in the first rank. The data bandwidth between the processors and the memory modules in the second rank is varied by varying the number of memory modules in the first rank that are used to access the memory module in the second set. Each of the memory modules includes several memory devices coupled to a memory hub. The memory hub includes a memory controller coupled to each memory device, a link interface coupled to a respective processor or memory module, and a cross bar switch coupling any of the memory controllers to any of the link interfaces.

Abstract: An integrated data accessing system having control apparatus for multi-directional data transmission is described. The integrated data accessing system includes a control apparatus, a plurality of communication interface engines. The control apparatus includes a plurality of bi-directional transmission modules, a control unit, a multi-directional transferring engine, and a memory unit. The control unit detects a source storage and a target storage. The multi-directional transferring engine selectively transfers the data content among storage units. The multi-directional transferring engine includes a first switch module, a second switch module, and a data buffer. The first switch module switches to the first bi-directional transmission module to select the source storage. The second switch module switches to the second bi-directional transmission module to select the target storage. The data buffer stores the data content transmitted from the source storage and the target storage.

Abstract: A method of managing IT resources when an IT resource managed by a coordinator is subject to a power-off request is provided. The method includes, in an event a sufficient quantity of resource statistics is present, analyzing resource statistics and operational policies to determine whether execution of the power-off request is currently, futuristically or potentially futuristically achievable with a threshold efficiency, and, in an event the power-off request is currently, futuristically or potentially futuristically achievable with the threshold efficiency, executing the power-off request, identifying a first time when the power-off request is achievable, instituting a first delay until then and, subsequently, executing the power-off request, and identifying a second time when the power-off request is potentially achievable, instituting a second delay until then and, subsequently, returning control to the analyzing operation, respectively.

Abstract: An arrangement for transferring message based communications between separate disjunctive components. The arrangement includes at least two components. At least a first component is arranged to provide services to at least one second component and/or to an operator of the loosely coupled system. At least one message bus is arranged to perform real-time transfers of communications from/to the at least one first component to/from the at least one second component. The at least one message bus is connected to or integrated in an internal communication backbone arranged with a communication member for establishing outgoing communication links. A predetermined message based interface is arranged relative to each of the components and the at least one message bus such that all communications between the at least one first component and the at least one second component are defined in the same single standardized message language.

Abstract: A method for controlling power consumption while maximizing processor performance. The method includes, for a time interval of operation in a first operational state, determining an amount of power consumed during by one or more cores of a processor, calculating, a power error based on the amount of power consumed in the time interval, obtaining a power error term for the interval by adding the power error to a power error term from a previous time interval, and comparing the power error term to at least a first error threshold. If the power error term is outside a range defined at least in part by the first error threshold, the method exits the first operational state and enters a second operational state. If the power error term is within the range defined at least in part by the first error threshold, operation continues in the first operational state.

Abstract: Mechanisms for priority control in resource allocation is provided. With these mechanisms, when a unit makes a request to a token manager, the unit identifies the priority of its request as well as the resource which it desires to access and the unit's resource access group (RAG). This information is used to set a value of a storage device associated with the resource, priority, and RAG identified in the request. When the token manager generates and grants a token to the RAG, the token is in turn granted to a unit within the RAG based on a priority of the pending requests identified in the storage devices associated with the resource and RAG. Priority pointers are utilized to provide a round-robin fairness scheme between high and low priority requests within the RAG for the resource.

Abstract: A method of interfacing between a universal serial bus (USB) host and a USB device. The USB host and the USB device include modules to process packets according to network protocols, instead of USB bus interfaces. Therefore, the USB device can be connected to the USB host even without a USB cable, and thus is not affected by the distance between the USB host and USB device.

Abstract: First and second counter circuits output a signal based on a trigger signal and a clock signal respectively. A selection circuit selects first to fourth signals as the trigger signal, the clock signal, the trigger signal and the clock signal. In a first output mode, an output circuit outputs signals exhibiting normal-phase and reversed-phase PWM waveforms based on both of the signals of the first and second counter circuits. In a second output mode, the output circuit outputs signals that are each based only on either of the signals of the first and second counter circuits.

Abstract: An IC includes a processing module, on-chip memory, one or more block input/output (I/O) interfaces for coupling to one or more off-chip block I/O devices, one or more character I/O interfaces for coupling to one or more off-chip character I/O devices when active, a main memory interface for coupling to off-chip main memory, a baseband processing module, an RF section, a processing module interface, and an IC bus structure. The processing module interface couples the processing module to an off-chip connection structure, wherein, when a handheld computing unit that includes the IC is docked to an extended computing unit, the off-chip connection structure couples the handheld computing unit to the extended computing unit such that the IC is in a docked mode.

Abstract: The present invention is a system and method for detecting the presence of a cable in a connector. The system may comprise one or more of the following features: (a) a first circuit contact; (b) a second circuit contact; (c) a first capacitive element; (d) an electrical ground; (e) a voltage source; and (f) a logical output. The second circuit contact may be connected to ground. The capacitive element may be driven to ground by connection of the first and second circuit contacts to corresponding cable contacts.

Abstract: A method of notifying asynchronous events to a host of a data storage system is presented. The method comprises the steps of: detecting an asynchronous event; generating an interrupt message in response to the detected asynchronous event; and communicating the generated interrupt message to the host.

Abstract: An information processing system including plural information processing devices multi-dimensionally connected with one another, where each of the information processing devices includes first and second receiving storage devices to store data allocated to first and second virtual channels in respective data transmitting and receiving directions, a virtual channel control unit to compare a position in a dimension of a destination information processing device with a position in the same dimension of an own information processing device, and if the comparison result indicates that the position of the own information processing device matches a position one information processing device before the position of the destination information processing device, change one of the first and the second virtual channels to the other one, and a data storage unit to store the allocated data in a corresponding one of the first and second storage devices.

Abstract: An information processing apparatus includes a first information processor, a plurality of second information processor, and a plurality of temperature detecting units detecting temperature in the vicinity of each of the plurality of second information processors. The first information processor includes an application program execution control unit controlling execution of an application program, a distributed processing control unit controlling distributed processing, a recording unit recording first information relating to temperature detected by the temperature detecting unit, and second information relating to the execution of the process of the second information processor, an anomaly detecting unit detecting an anomaly in the temperature detected by the temperature detecting unit, and an anomaly-time control unit controlling the distributed processing of the distributed processing control unit in response to the temperature anomaly detected by the anomaly detecting unit.

Abstract: A power supply voltage regulator circuit including a power supply circuit which switches to a first through a fourth state; the first state being the state wherein voltage is supplied to neither a normal circuit nor a backup system circuit based on the combination of logic for the normal circuit power control signal, the second state being the state wherein a primary power supply voltage is supplied to the normal circuit and a secondary power supply voltage is supplied to the backup system circuit, the third state being the state wherein voltage is not supplied to the normal circuit and the secondary power supply voltage is supplied to the backup system circuit, the fourth state being the state wherein the primary power supply voltage is supplied to both the normal circuit and the backup system circuit.

Abstract: A method and system for bus arbitration to be used in a system having a plurality of data handling units (110a, . . . , 110d) and a shared bus (140) with a plurality of data-lines. The invention provides a method and an system to carry out the method, having steps of; receiving data transfer requests from the data handling units; selecting a set of data transfer requests the allowance of which serves a maximum number of data handling units and utilizes a maximum number of data-lines, and; allowing the data handling units that issued said selected set of data transfer requests to access said bus in a single bus cycle.

Abstract: Embodiments of apparatuses, systems, and methods are described for communicating information between functional blocks of a system across a communication fabric. Rate logic may couple to the communication fabric. The rate logic is configured to determine a data bandwidth difference between a first data bandwidth capability of the sending device and the lower of 1) a second data bandwidth capability of the sending device or 2) a third data bandwidth capability of the communication fabric.