Abstract: A power monitoring system for electrical panels providing power, received from one or more power sources, to multiple current conductors. The power monitoring system preferably includes a plurality of sensors affixed to a support. A portion of each sensor defines an opening through which a current conductor may be extended.

Abstract: An integrated test circuit arrangement is provided that contains integrated test structures, at least one integrated heating element, an integrated detection unit, an integrated supply unit, and a control unit. The integrated detection unit detects at least one physical property for each of the test structures. The integrated supply unit supplies each of the test structures with a current or a voltage in switchable fashion independently of one another. The control unit is connected to outputs of the detection unit on an input side and controls the supply unit dependent on the detection results.

Abstract: Disclosed is a memory application tester for testing a semiconductor memory device. A plurality of motherboards of the tester are vertically mounted and connected to memory devices to be tested mounted on an interface board via a HiFix board so that a memory application tester may test more memory device simultaneously, and a limit in the trace length due to the integration of the motherboards is effectively solved.

Abstract: An improved voltage test system.

Abstract: The present invention is a novel method and computer program product which utilizes an interface capacitor formed by the metal of the probe tip, a dielectric layer, such as an oxide, formed by a contaminant on a solder bump and the metal of the solder bump. The interface capacitor forms a capacitive divider with the inherent capacitances of the automatic test equipment and the device under test (DUT). The voltage characteristics of the capacitive divider are used to drive voltage signals across the interface capacitor to test the DUT. In either direction (i.e. from the automatic test equipment to the DUT or vice versa), by altering the voltage output high amplitude of the driver and/or the voltage input high amplitude of the load, the DUT is validly tested through the interface capacitor. Thus, even if all I/O bumps have an oxide layer, the device may still be validly tested.

Abstract: A guide for tip to transmission path contact includes a guide insulator having at least one passageway defined therein. Each passageway has a tip passageway end and a transmission path passageway end. The tip passageway end is suitable for at least partially accommodating the tip of a probing head. The transmission path passageway end is suitable for at least partially accommodating a transmission path of a circuit board component. The tip contacts a transmission path through a passageway when the transmission path is positioned in the transmission path passageway end and the tip is positioned within the tip passageway end.

Abstract: A plurality of resistors is connected to a plurality of output terminals of a semiconductor integrated circuit, respectively, and a predetermined voltage is applied to the plurality of resistors. Also, a predetermined operation pattern signal used to test functions of the semiconductor integrated circuit is input to a plurality of input terminals of the semiconductor integrated circuit. Thus, a total sum of amounts of currents caused to flow through the plurality of resistors, respectively, is measured. The total sum of amounts of currents thus measured is compared with a normal value of a total sum of amounts of currents which are measured in a non-defective sample which is used instead of the semiconductor integrated circuit and is verified in advance to normally operate. It is judged based on the comparison results whether or not the semiconductor integrated circuit is normal.

Abstract: An interconnect for testing semiconductor components includes a substrate, and contacts on the substrate for making temporary electrical connections with bumped contacts on the components. Each contact includes a recess and a pattern of leads cantilevered over the recess configured to electrically engage a bumped contact. The leads are adapted to move in a z-direction within the recess to accommodate variations in the height and planarity of the bumped contacts. In addition, the leads can include projections for penetrating the bumped contacts, a non-bonding outer layer for preventing bonding to the bumped contacts, and a curved shape which matches a topography of the bumped contacts. The leads can be formed by forming a patterned metal layer on the substrate, by attaching a polymer substrate with the leads thereon to the substrate, or be etching the substrate to form conductive beams.

Abstract: Systems and methods for detecting errors in communication networks are described. When an interface component is potentially defective, a rules engine performs diagnostic testing to determine if the interface component is defective. During diagnostics, the rules engine tests a protection interface card to determine if it is defective before determining if the interface component is defective.

Abstract: An integrated circuit (IC) package testing apparatus integrates a temperature sensor, heater (or cooler), and controller within a single modular unit. The controller is a microprocessor embedded within the modular unit and in communication with the sensor and heater. The controller allows a selected testing temperature to be input by a user via a communications link to the controller. Each IC package has its testing temperature individually controlled by a controller. The module is easily attached and removed from an open-top socket through the use of latches on the testing socket. Many IC packages can be quickly placed and removed from testing sockets when a matrix of sensors and heaters (or coolers) are located on a single top attach plate with the sensors and heaters (or coolers) individually spring-loaded on the single top attach plate.

Abstract: A system or apparatus for monitoring an Integrated Circuit (IC) chip, comprises: a sense circuit at least partially constructed on the IC chip and configured to produce one or more sense signals each indicative of a corresponding process-dependent circuit parameter of the IC chip; and a digitizer module configured to produce, responsive to the one or more sense signals, one or more digitized signals each representative of a corresponding one of the sense signals. A controller is configured to determine a value of one or more of the process-dependent circuit parameters based on one or more of the digitized signals.

Abstract: An electric power usage and reporting system for collecting electric power demand readings from multiple properties which may be either commonly owned or leased by the same company, processing the demand data to generate KWH and KW information on an individual property basis and on a combined properties basis and generating a report including the KWH usage and KW demand information. The report includes information on electric power KWH usage and KW demand in the aggregate and with respect to each property and includes information on coincident KW demand in the aggregate and with respect to each property.

Abstract: A probe card includes a main substrate, a main reinforcing plate attached to the upper surface of the main substrate, a sub-reinforcing plate attached to the upper surface of the main reinforcing plate, and coupling force adjusting means that couples the main reinforcing plate with the sub-reinforcing plate and adjusts the coupling force therebetween. The coupling force adjusting means has a plurality of threaded holes provided at intersections of a plurality of imaginary concentric circles, which is provided with a distance from a center of a probe card on a surface of the sub-reinforcing plate, and a plurality of imaginary straight lines, which is provided radially from the center at an predetermined angle; a plurality of screw holes provided at same intersections on a surface of the main reinforcing plate; and a plurality of coupling screws threaded selectively into the threaded holes 23a and the screw holes.

Abstract: An optical sampling apparatus has an electron beam generating apparatus which generates an electron beam by irradiating a cathode with an optical signal, a deflection electrode which deflects the generated electron beam, a sampling slit which transmits a part of the deflected electron beam, and a charge detection section which detects the quantity of charges or accumulated current of the transmitted electron beam. It is possible to perform accurate sampling in a high band.

Abstract: A system and method measures parameters associated with an inductor such as in a switching converter. The inductance value can be determined by monitoring voltages and currents associated with the inductor when a measurement mode is activated. In one example, the measurement is provided by a signal processing system that includes an analog differentiator. In another example, the measurement is provided by a signal processing system that converts the analog measurement voltages into digital quantities that are analyzed in the digital domain. The value of the inductance value is determined by calculating of ?VL and ?IL/?t. The saturation point in the inductance is located by measuring the change in slew rate of the inductance during the measurement mode. Average values for the inductor and the slew rate can be determined using digital techniques. Other parameters such as current limit and on-time of the inductor can be adjusted by this methodology.

Abstract: Pixel units are disposed in a display region of a substrate, and scan lines and data lines are used to control the pixel units. Inner short ring includes a first segment, a second segment and a connecting segment connecting both segments. The gates and sources of the first and second active device connect with the first and second segments respectively, and the drains connect with the connecting segment. The gates and sources of part of the third active devices connect with the first segment, and the drains connect with the odd scan lines. The gates and sources of other third active devices connect with the second segment, and the drains connect with the even scan lines. The gates of the fourth active devices connect with connecting lines, and the sources connect with data testing lines, and the drains connect with the odd and even data lines respectively.

Abstract: A holding side contact arm (317) for holding an IC to be tested is positioned on the optical axis (OP) of an alignment CCD camera (326) of an alignment device (320), the IC to be tested is inserted to a first opening (321a) formed on an alignment movable portion (321), and a contact member (317d) of the holding side contact arm (317) is brought to contact the alignment movable portion (321). Then, an alignment amount for correcting a position of the IC to be tested is calculated by taking an image by the camera (326) and performing image processing. A lock-and-free means (318) provided to a first contact arm (315a1) is made to be in a non-restricted state, a movable portion driving device (322) is driven based on the alignment amount, and the holding side contact arm (317) contacting the alignment movable portion (321) is moved with respect to a root side contact arm (316), so that alignment of a position of the IC to be tested is performed.

Abstract: A Hall effect generator chip is mounted between adjacent ends of an annular, horseshoe spacer of nonmagnetic material. The generator is sensitive to the flux density (B field) tangential to its top and bottom surfaces. The spacer and generator are sandwiched between ferromagnetic rings, each having a small air gap overlying/underlying the generator. A circuit including the generator supplies an output linearly proportional to the current of an adjacent conductor with reduced hysteresis and small variability over a temperature range.

Abstract: A network analyzing apparatus that analyzes the network properties of a device under test by applying reference signals to a device under test by frequency sweeping or power sweeping comprises input device for inputting the sweep range and sweep interval of these reference signals as well as the center coordinates and radius of a test circle for testing this device under test; a measurement apparatus for measuring the network properties of this device under test and obtaining measurements for n number of measurement points determined from this sweep range and sweep interval; and a testing apparatus, with this testing apparatus finding the difference between this measurement and center coordinates and, referring to this difference and this radius, determining that this measurement that has been read passes the test if the magnitude of this referred difference is no greater than this referred radius, or is less than this referred radius.

Abstract: A gate capacitance of a MOS transistor is determined by (a) measuring the gate capacitance and dissipation factor; (b) obtaining a channel resistance and a tunneling resistance; (c) setting an initial capacitance and an error dissipation factor; (d) calculating a direct dissipation factor using the channel resistance, the tunneling resistance, and the initial capacitance; (e) calculating a calculated dissipation factor using the error dissipation factor, the direct dissipation factor, and the measured dissipation factor; (f) calculating a calculated capacitance using the channel resistance, the tunneling resistance, the initial capacitance, the error dissipation factor, and the measured dissipation factor; and (g) detecting the initial capacitance as an accurate gate capacitance of the transistor if it is determined that the calculated capacitance is equal to the measured capacitance and the calculated dissipation factor is equal to the measured dissipation factor, and otherwise repeating steps (c) through (g