Abstract: A method for fabricating a nanosheet semiconductor structure includes forming a first nanosheet field effect transistor (FET) structure having a first inner spacer of a first material and a second nanosheet FET structure having second inner spacer of a second material. The first material is different than the second material.

Abstract: An integrated circuit device includes a pad layer having a body portion with a first doping type laterally adjacent to a drift region portion with a second doping type, a trench formed in the pad layer, the trench extending through an interface of the body portion and the drift region portion, a gate formed in the trench and over a top surface of the pad layer along the interface of the body portion and the drift region portion, an oxide formed in the trench on opposing sides of the gate, and a field plate embedded in the oxide on each of the opposing sides of the gate.

Abstract: To provide a transistor including an oxide semiconductor layer and having electric characteristics required depending on an intended use and provide a semiconductor device including the transistor, in a transistor in which a semiconductor layer, source and drain electrode layers, a gate insulating film, and a gate electrode are stacked in this order over an oxide semiconductor insulating film, an oxide semiconductor stack layer which includes at least two oxide semiconductor layers with energy gaps different from each other and a mixed region therebetween is used as the semiconductor layer.

Abstract: A method of manufacturing a multichip package structure includes providing a substrate body; placing a plurality of light-emitting chips on the substrate body, the light-emitting chips being electrically connected to the substrate body; surroundingly forming surrounding liquid colloid on the substrate body to surround the light-emitting chips; naturally drying an outer layer of the surrounding liquid colloid at a predetermined room temperature to form a semidrying surrounding light-reflecting frame, the semidrying surrounding light-reflecting frame having a non-drying surrounding colloid body disposed on the substrate body and a dried surrounding colloid body totally covering the non-drying surrounding colloid body; and then forming a package colloid body on the substrate body to cover the light-emitting chips, the semidrying surrounding light-reflecting frame contacting and surrounding the package colloid body.

Abstract: A top-emission organic EL display device includes a substrate, pixel electrodes, auxiliary electrode, insulating layer formed between the pixel electrodes and includes an opening to expose the auxiliary electrode, organic EL layer formed on the pixel electrodes and includes organic layers, at least one formed on the auxiliary electrode, a contact portion being an opening of the organic layer formed on the auxiliary electrode, and transparent electrode layer formed on the organic EL layer and the contact portion. When an insulating layer overlap distance between the contact portion and pixel electrode adjacent to the contact portion with respect to the pixel electrode is regarded as “a” and an insulating layer overlap distance between the contact portion and pixel electrode adjacent to the contact portion with respect to the auxiliary electrode is regarded as “b”, at least one of “a” and “b” is equal to or greater than 2 ?m.

Abstract: A display device includes a display area and a terminal area formed outside the display area. The display area has a plurality of scanning lines and a plurality of video signal lines that cross the scanning lines. The terminal area has a first terminal having a semiconductor chip connected thereto, a first line, a second line, and an inspection thin-film transistor. The inspection thin-film transistor has a gate electrode connected to the first line, a source electrode connected to the second line, and a drain electrode. The first terminal is connected to any of the plurality of scanning lines and the plurality of video signal lines.

Abstract: A component, e.g., interposer has first and second opposite sides, conductive elements at the first side and terminals at the second side. The terminals can connect with another component, for example. A first element at the first side can comprise a first material having a thermal expansion coefficient less than 10 ppm/° C., and a second element at the second side can comprise a plurality of insulated structures separated from one another by at least one gap. Conductive structure extends through at least one insulated structure and is electrically coupled with the terminals and the conductive elements. The at least one gap can reduce mechanical stress in connections between the terminals and another component.

Abstract: A silicon carbide semiconductor device includes trenches formed in a lattice shape on the surface of a silicon carbide substrate on which a semiconductor layer is formed, and gate electrodes formed inside of the trenches via a gate insulating film. The depth of the trenches is smaller in a portion where the trenches are crossingly formed than in a portion where the trenches are formed in parallel to each other. Consequently, the silicon carbide semiconductor device is obtained that increases a withstand voltage between the gate electrodes and corresponding drain electrodes on the semiconductor device rear surface to prevent dielectric breakdown and, at the same time, has a large area of the gate electrodes, high channel density per unit area, and low ON resistance.

Abstract: After formation of a disposable gate structure, a raised active semiconductor region includes a vertical stack, from bottom to top, of an electrical-dopant-doped semiconductor material portion and a carbon-doped semiconductor material portion. A planarization dielectric layer is deposited over the raised active semiconductor region, and the disposable gate structure is replaced with a replacement gate structure. A contact via cavity is formed through the planarization dielectric material layer by an anisotropic etch process that employs a fluorocarbon gas as an etchant. The carbon in the carbon-doped semiconductor material portion retards the anisotropic etch process, and the carbon-doped semiconductor material portion functions as a stopping layer for the anisotropic etch process, thereby making the depth of the contact via cavity less dependent on variations on the thickness of the planarization dielectric layer or pattern factors.

Abstract: This invention discloses a semiconductor device disposed in a semiconductor substrate. The semiconductor device includes a first semiconductor layer of a first conductivity type on a first major surface. The semiconductor device further includes a second semiconductor layer of a second conductivity type on a second major surface opposite the first major surface. The semiconductor device further includes an injection efficiency controlling buffer layer of a first conductivity type disposed immediately below the second semiconductor layer to control the injection efficiency of the second semiconductor layer.

Abstract: In at least one embodiment, a method is designed to produce optoelectronic semiconductor chips. A carrier assembly, which is a sapphire wafer, is produced. A semiconductor layer sequence is applied to the carrier assembly. The carrier assembly and the semiconductor layer sequence are divided into the individual semiconductor chips. The dividing is implemented by producing a multiplicity of selectively etchable material modifications in the carrier assembly in separation region(s) by focused, pulsed laser radiation. The laser radiation has a wavelength at which the carrier assembly is transparent. The dividing includes wet chemically etching the material modifications, such that the carrier assembly is singulated into individual carriers for the semiconductor chips solely by the wet chemical etching or in combination with a further material removal method.

Abstract: There is provided a semiconductor light emitting device including a conductive substrate, a first electrode layer, an insulating layer, a second electrode layer, a second semiconductor layer, an active layer, and a first semiconductor layer that are sequentially stacked. The contact area between the first electrode layer and the first semiconductor layer is 3% to 13% of the total area of the semiconductor light emitting device, and thus high luminous efficiency is achieved.

Abstract: An element manufacturing method and apparatus for efficiently manufacturing an element such as an organic semiconductor element. First, an intermediate product that includes a substrate and a protrusion extending in a normal direction of the substrate is provided. Next, in a stacking chamber conditioned to a vacuum environment, a stacked structure is formed by continuously stacking a lid member on the intermediate product at a side where the protrusion is provided. After this operation, the stacked structure is transported from the stacking chamber to a first pressure chamber coupled to the stacking chamber and conditioned to a first pressure higher than the pressure in the vacuum environment. Next, the stacked structure is further transported from the first pressure chamber to a separation chamber coupled to the first pressure chamber and conditioned to a vacuum environment, and then the stacked structure is separated into the intermediate product and the lid member.

Abstract: A semiconductor device and a manufacturing method thereof is disclosed in which the semiconductor device includes a p-type anode layer formed by a transition metal acceptor transition, and the manufacturing process is significantly simplified without the breakdown voltage characteristics deteriorating. An inversion advancement region inverted to a p-type by a transition metal acceptor transition, and in which the acceptor transition is advanced by point defect layers, is formed on the upper surface of an n-type drift layer. The inversion advancement region configures a p-type anode layer of a semiconductor device of the invention. The transition metal is, for example, platinum or gold. An n-type semiconductor substrate with a concentration higher than that of the n-type drift layer is adjacent to the lower surface of the n-type drift layer.

Abstract: The present disclosure provides an integrated circuit. The integrated circuit includes a semiconductor substrate; and a passive polysilicon device disposed over the semiconductor substrate. The passive polysilicon device further includes a polysilicon feature; and a plurality of electrodes embedded in the polysilicon feature.

Abstract: In a non-volatile memory in which writing/erasing is performed by changing a total charge amount by injecting electrons and holes into a silicon nitride film serving as a charge accumulation layer, in order to realize a high efficiency of a hole injection from a gate electrode, the gate electrode of a memory cell comprises a laminated structure made of a plurality of polysilicon films with different impurity concentrations, for example, a two-layered structure comprising a p-type polysilicon film with a low impurity concentration and a p?-type polysilicon film with a high impurity concentration deposited thereon.

Abstract: A device includes a semiconductor substrate and implant isolation region extending from a top surface of the semiconductor substrate into the semiconductor substrate surrounding an active region. A gate dielectric is disposed over an active region of the semiconductor substrate, wherein the gate dielectric extends over the implant isolation region. A gate electrode is disposed over the gate dielectric and an end cap dielectric layer is between the gate dielectric and the gate electrode over the implant isolation region.

Abstract: A switched-capacitor DC-to-DC converter includes a logic cell and a capacitor cell vertically overlapping with the logic cell. The logic cell has a plurality of active elements disposed over a first substrate. The capacitor cell has a capacitor over a second substrate. A first interlayer insulation layer disposed over the first substrate is bonded to a second interlayer insulation layer disposed over the second substrate. A first through via connected to any one of interconnection patterns of the logic cell and a second through via connected to a lower electrode pattern of the capacitor cell are connected to each other through a first external circuit pattern. A third through via connected to an upper electrode pattern of the capacitor cell and a fourth through via connected to another one of the interconnection patterns of the logic cell are connected to each other through a second external circuit pattern.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

Abstract: A transparent conductive thin film and an electronic device including the same are disclosed, the transparent conductive thin film including a titanium nitride or a zirconium nitride having a heterometal element selected from zinc (Zn), gallium (Ga), indium (In), and a combination thereof.