Patents Examined by Jerome Jackson
  • Patent number: 9666588
    Abstract: A non-volatile memory cell formed using damascene techniques includes a floating gate electrode that includes a recess lined with a control gate dielectric and filled with the control gate electrode material. The control gate material is a composite ONO, oxide-nitride-oxide sandwich dielectric in one embodiment. The floating gate transistors of the non-volatile memory cell include a high gate coupling ratio due to the increased area between the floating gate electrode and the control gate electrode.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Yu Chiu, Hung-Che Liao
  • Patent number: 9666686
    Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
    Type: Grant
    Filed: December 1, 2015
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chii-Horng Li, Hsueh-Chang Sung, Kun-Mu Li, Tze-Liang Lee, Tsz-Mei Kwok
  • Patent number: 9659871
    Abstract: Provided is a semiconductor device including a substrate with a plurality of logic cells, transistors provided in the plurality of logic cells, contact plugs connected to electrodes of the transistors, first via plugs in contact with top surfaces of the contact plugs, and first wires in contact with top surfaces of the first via plugs. The first wires may include a common conductive line connected to the plurality of logic cells through the contact plugs, and all of the first wires may be shaped like a straight line extending parallel to a specific direction.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: May 23, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Raheel Azmat, Rwik Sengupta, Chulhong Park, Kwanyoung Chun
  • Patent number: 9660091
    Abstract: A thin film transistor (TFT) and a method of driving the same are disclosed. The TFT includes: an active layer; a bottom gate electrode disposed below the active layer to drive a first region of the active layer; and a top gate electrode disposed on the active layer to drive a second region of the active layer. The TFT controls the conductivity of the active layer by using the bottom gate electrode and the top gate electrode.
    Type: Grant
    Filed: August 6, 2014
    Date of Patent: May 23, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eok-su Kim, Myung-kwan Ryu, Kyoung-seok Son, Sung-hee Lee
  • Patent number: 9653589
    Abstract: A semiconductor multi-layer substrate includes a substrate made of Si and a multi-layer semiconductor layer. The multi-layer semiconductor layer includes an active layer made of a nitride semiconductor, a first warp control layer being formed between the substrate and the active layer and giving a predetermined warp to the substrate, and a second warp control layer made of a nitride semiconductor of which amount of an increase in a warp per a unit thickness is smaller than an amount of increase in the warp per a unit thickness of the first warp control layer. A total thickness of the multi-layer semiconductor layer is equal to or larger than 4 ?m.
    Type: Grant
    Filed: September 10, 2014
    Date of Patent: May 16, 2017
    Assignees: FURUKAWA ELECTRIC CO., LTD., FUJI ELECTRIC CO., LTD.
    Inventors: Kazuyuki Umeno, Tatsuyuki Shinagawa, Keishi Takaki, Ryosuke Tamura, Shinya Ootomo
  • Patent number: 9650243
    Abstract: A wafer seal ring may be formed on a first and/or a second wafer. One or both of the first and/or second wafers may have one or more dies formed thereon. The wafer seal ring may be formed to surround the dies of a corresponding wafer. One or more die seal rings may be formed around the one or more dies. The wafer seal ring may be formed to a height that may be approximately equal to a height of one or more die seal rings formed on the first and/or second wafer. The wafer seal ring may be formed to provide for eutectic or fusion bonding processes. The first and second wafers may be bonded together to form a seal ring structure between the first and second wafers. The seal ring structure may provide a hermetic seal between the first and second wafers.
    Type: Grant
    Filed: March 10, 2016
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Ying Chen, Yi Hsun Chiu, Ching-Hou Su, Chyi-Tsong Ni
  • Patent number: 9653286
    Abstract: GaN based nanowires are used to grow high quality, discreet base elements with c-plane top surface for fabrication of various semiconductor devices, such as diodes and transistors for power electronics.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: May 16, 2017
    Assignee: HEXAGEM AB
    Inventors: Jonas Ohlsson, Mikael Bjork
  • Patent number: 9653374
    Abstract: A structure includes a thermal interface material, and a Perforated Foil Sheet (PFS) including through-openings therein, with a first portion of the PFS embedded in the thermal interface material. An upper layer of the thermal interface material is overlying the PFS, and a lower layer of thermal interface material is underlying the PFS. The thermal interface material fills through-openings in the PFS.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Wensen Hung
  • Patent number: 9653443
    Abstract: An embodiment device includes a first die, a second die electrically connected to the first die, and a heat dissipation surface on a surface of the second die. The device further includes a package substrate electrically connected to the first die. The package substrate includes a through-hole, and the second die is at least partially disposed in the through hole.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: May 16, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung Wei Cheng, Tsung-Ding Wang, Mirng-Ji Lii, Chien-Hsun Lee
  • Patent number: 9647109
    Abstract: According to one embodiment, the fifth semiconductor region contacts the first semiconductor region. The metal region is provided on the fifth semiconductor region. The first insulating film extends in a thickness direction of the semiconductor layer. The first insulating film is adjacent to the fourth semiconductor region, the third semiconductor region, the second semiconductor region, and the first semiconductor region. The second insulating film extends in the thickness direction of the semiconductor layer. The second insulating film is provided between the fourth semiconductor region and the first conductive unit, between the third semiconductor region and the first conductive unit, and between the second semiconductor region and the first conductive unit.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: May 9, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroaki Tajima, Kazuaki Yamaura
  • Patent number: 9647155
    Abstract: The disclosure provides a photo-detection device for use in long-wave infrared detection and a method of fabrication. The device comprises a GaSb substrate, a photo absorbing layer comprising InAs/InAsSb superlattice type-II, a barrier layer comprising AlAsSb, and a contact layer comprising InAs/InAsSb superlattice type-II. The barrier layer is configured to allow minority carrier holes current flow while blocking majority carrier electrons current flow between the photo-absorbing and contact layers. The disclosure further provides a method of producing the photo-detector using photolithography which includes selective etching of the contact layer that stops on the top of the barrier so no etching is made to the barrier layer so the barrier may operate as a passivator too. The disclosure presents an x-ray and photoluminescence results for InAs/InAsSb superlattice type-II material.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: May 9, 2017
    Inventor: Shimon Maimon
  • Patent number: 9640686
    Abstract: An electro-optical device can include a plurality of nanocrystals positioned between a first electrode and a second electrode.
    Type: Grant
    Filed: January 29, 2014
    Date of Patent: May 2, 2017
    Assignee: Massachusetts Institute of Technology
    Inventors: Moungi Bawendi, Venda J. Porter, Marc Kastner, Tamar Mentzel
  • Patent number: 9640648
    Abstract: A semiconductor device includes a first semiconductor layer formed on a substrate; a second semiconductor layer and a third semiconductor layer formed on the first semiconductor layer; a fourth semiconductor layer formed on the third semiconductor layer; a gate electrode formed on the fourth semiconductor layer; and a source electrode and a drain electrode formed in contact with the second semiconductor layer. The third semiconductor layer and the fourth semiconductor layer are formed in an area immediately below the gate electrode, the fourth semiconductor layer is formed with a p-type semiconductor material, and the second semiconductor layer and the third semiconductor layer are formed with AlGaN, and the third semiconductor layer has a lower composition ratio of Al than that of the second semiconductor layer.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: May 2, 2017
    Assignee: Transphorm Japan, Inc.
    Inventor: Toshihide Kikkawa
  • Patent number: 9640607
    Abstract: According to an embodiment of the invention there may be provided a die that may include a first capacitor layer that comprises (a) a first capacitor conductive plate, and (b) a first capacitor layer dielectric material that partially surrounds the first capacitor conductive plate; a first conductor; an intermediate metal layer that comprises (a) an intermediate metal layer conductor that is made of Copper, and (b) an intermediate metal layer dielectric material that partially surrounds the intermediate metal layer conductor; wherein the first conductor is positioned between a substrate of the die and the intermediate metal layer; a redistribution layer that comprises (a) a redistribution layer conductor that is electrically coupled to an interface pad of the die, (b) a second capacitor conductive plate, and (c) a redistribution layer dielectric material that partially surrounds the redistribution layer conductor and the second capacitor conductive plate; wherein a certain portion of the intermediate metal la
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: May 2, 2017
    Assignee: TOWER SEMICONDUCTOR LTD.
    Inventor: Sharon Levin
  • Patent number: 9640718
    Abstract: According to one embodiment, a method for manufacturing a display element is disclosed. The method can include forming a peeling layer, forming a resin layer, forming a barrier layer, forming an interconnect layer, forming a display layer, and removing. The peeling layer is formed on a major surface of a base body. The major surface has first, second, and third regions. The peeling layer includes first, second, and third peeling portions. The resin layer is formed on the peeling layer. The resin layer includes first and second resin portions. The barrier layer is formed on the first, second, and third peeling portions. The interconnect layer is formed on the barrier layer. The display layer is formed on the interconnect layer. The first peeling portion is removed from the first resin portion and the second peeling portion is removed from the second resin portion.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: May 2, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kentaro Miura, Tatsunori Sakano, Tomomasa Ueda, Nobuyoshi Saito, Shintaro Nakano, Yuya Maeda, Hajime Yamaguchi
  • Patent number: 9640612
    Abstract: A semiconductor device includes: a first conductivity type semiconductor substrate; and a plurality of second conductivity type semiconductor regions, the respective second conductivity type semiconductor regions being embedded in a plurality of stripe shaped trenches formed in the semiconductor substrate so that the respective second conductivity type semiconductor regions are extended in the row direction or the column direction in parallel with a first principal surface of the semiconductor substrate and are spaced in a fixed gap mutually. The semiconductor substrate and the plurality of the semiconductor regions are depleted by a depletion layer extended in the direction in parallel to the first principal surface from a plurality of pn junction interfaces, and the respective pn junction interfaces are formed between the semiconductor substrate and the plurality of the semiconductor regions.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: May 2, 2017
    Assignee: ROHM CO., LTD.
    Inventor: Shoji Higashida
  • Patent number: 9638378
    Abstract: Provided is a light emitting apparatus. The light emitting apparatus includes a substrate; a light emitting device on the substrate; a fluorescent layer formed on the substrate and the light emitting device to surround the light emitting device; an encapsulant resin layer formed on the substrate and the fluorescent layer to surround the fluorescent layer; and a lens disposed on the light emitting device and supported by the substrate, wherein the lens includes a lens body having a first recess formed at a center of a top surface of the lens body and a second recess formed at a center of a bottom surface of the lens body, and a lens supporter provided at the bottom surface of the lens body to support the lens body such that the lens body is spaced apart from the substrate.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: May 2, 2017
    Assignee: LG INNOTEK CO., LTD.
    Inventors: Sang Won Lee, Gyu Hyeong Bak
  • Patent number: 9634155
    Abstract: The invention relates to a method for producing an electrical terminal support for an optoelectronic semiconductor body, comprising the following steps: providing a carrier assembly (1), which comprises a carrier body (11), an intermediate layer (12) arranged on an outer surface (111) of the carrier body (11), and a use layer (13) arranged on the intermediate layer (12); introducing at least two openings (4), which are mutually spaced in the lateral direction (L), in the use layer (13) via an outer surface (131) of the use layer (13), wherein the openings extend completely through the use layer (13) in the vertical direction (V); electrically insulating lateral surfaces (41) of the openings (4) and of the outer face (131) of the use layer (13); arranging electrically conductive material (6) at least in the openings (4), wherein after completion of the terminal carrier (100), the electrically conductive material (6) has an interruption (U) in the progression thereof along the outer surface (131) of the use lay
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: April 25, 2017
    Assignee: OSRAM OPTO SEMICONDUCTORS GMBH
    Inventor: Andreas Plössl
  • Patent number: 9634105
    Abstract: A quantum nano-tip (QNT) thin film, such as a silicon nano-tip (SiNT) thin film, for flash memory cells is provided to increase erase speed. The QNT thin film includes a first dielectric layer and a second dielectric layer arranged over the first dielectric layer. Further, the QNT thin film includes QNTs arranged over the first dielectric layer and extending into the second dielectric layer. A ratio of height to width of the QNTs is greater than 50 percent. A QNT based flash memory cell and a method for manufacture a SiNT based flash memory cell are also provided.
    Type: Grant
    Filed: January 14, 2015
    Date of Patent: April 25, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsu-Hui Su, Chih-Ming Chen, Chia-Shiung Tsai, Chung-Yi Yu, Szu-Yu Wang
  • Patent number: 9633899
    Abstract: The invention provides a method for patterning a graphene layer and a method for manufacturing a display substrate. The method for patterning a graphene layer comprises: forming an isolation layer on a graphene layer; forming a photoresist layer on the isolation layer; patterning the photoresist layer; etching the isolation layer according to the patterned photoresist layer to form a patterned isolation layer; etching the graphene layer according to the patterned photoresist layer to form a patterned graphene layer; and removing the patterned isolation layer. In the method of the invention, the unfavorable condition of the prior art may be avoided that a graphene film sloughs off or a photoresist remains on a graphene film when a photoresist material is peeled off, and the product yield can be improved in the case that the production cost is controlled.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: April 25, 2017
    Assignee: BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Shi Shu, Zhijun Lv, Jingxia Gu, Yue Shi, Fangzhen Zhang, Bing Sun, Chuanxiang Xu