Patents Examined by Jerome Jackson
  • Patent number: 9583560
    Abstract: A power semiconductor device of stripe cell geometry including a substrate, a plurality of striped power semiconductor units, and a guard ring structure is provided. The substrate has an active area and a termination area surrounding the active area defined thereon. The striped semiconductor unit includes a striped gate conductive structure. The striped semiconductor units are located in the active area. The guard ring structure is located in the termination area and includes at least a ring-shaped conductive structure surrounding the striped power semiconductor units. The ring-shaped conductive structure and the striped gate conductive structures are formed on the same conductive layer, and at least one of the striped gate conductive structures is separated from the nearby ring-shaped conductive structure and electrically connected to the nearby ring-shaped conductive structure through the gate metal pad.
    Type: Grant
    Filed: March 4, 2015
    Date of Patent: February 28, 2017
    Assignee: UBIQ SEMICONDUCTOR CORP.
    Inventors: Kao-Way Tu, Yi-Yun Tsai, Yuan-Shun Chang
  • Patent number: 9577205
    Abstract: An organic light-emitting device including a first light-emitting region, a second light-emitting region, and a third light-emitting region. The organic light-emitting device includes a substrate; a first electrode layer on the substrate; a hole injection layer on the first electrode layer; a common emission layer on the hole injection layer; a first resonance assistance layer on the common emission layer in the first light-emitting region and a second resonance assistance layer on the common emission layer in the second light-emitting region.
    Type: Grant
    Filed: September 14, 2013
    Date of Patent: February 21, 2017
    Assignee: Samsung Display Co., Ltd.
    Inventors: Byeong-Wook Yoo, Sang-Woo Pyo, Ha-Jin Song, Hyo-Yeon Kim, Hye-Yeon Shim, Ji-Young Kwon, Heun-Seung Lee, Ji-Hwan Yoon
  • Patent number: 9576952
    Abstract: Integrated circuits and fabrication methods are provided. The integrated circuit includes: a varying gate structure disposed over a substrate structure, the varying gate structure including a first gate stack in a first region of the substrate structure, and a second gate stack in a second region of the substrate structure; a first field-effect transistor in the first region, the first field-effect transistor including the first gate stack and having a first threshold voltage; and a second field-effect transistor in the second region, the second field-effect transistor including the second gate stack and having a second threshold voltage, where the first threshold voltage is different from the second threshold voltage. The methods include providing the varying gate structure, the providing including: sizing layer(s) of the varying gate structure with different thickness(es) in different region(s).
    Type: Grant
    Filed: February 25, 2014
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Manoj Joshi, Manfred Eller, Richard J. Carter, Srikanth Balaji Samavedam
  • Patent number: 9570670
    Abstract: Provided are a magnetic memory device and a method of fabricating the same. The device may include a magnetic tunnel junction including a lower magnetic structure, an upper magnetic structure, and a tunnel barrier interposed therebetween. The tunnel barrier may have a width greater than that of the lower magnetic structure.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: February 14, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: ChanJin Park, Woojin Kim, Hyungjoon Kwon, Soonoh Park, Jongchul Park, Sechung Oh
  • Patent number: 9570465
    Abstract: An integrated circuit, including: a first cell, including: FDSOI transistors; a UTBOX layer lying beneath the transistors; a first well lying beneath the insulator layer and beneath the transistors, the first well having a first type of doping; a first ground plane having a second type of doping, located beneath one of the transistors and between the insulator layer and the first well; a first STI separating the transistors and crossing the insulator layer; a first conductive element forming an electrical connection between the first well and the first ground plane, located under the first STI; a second cell including a second well; a second STI separating the cells, crossing the insulator layer and reaching the bottom of the first and second wells.
    Type: Grant
    Filed: February 28, 2013
    Date of Patent: February 14, 2017
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, INTERNATIONAL BUSINESS MACHINES CORPORATION, STMicroelectronics, Inc.
    Inventors: Maud Vinet, Kangguo Cheng, Bruce Doris, Laurent Grenouillet, Ali Khakifirooz, Yannick Le Tiec, Qing Liu
  • Patent number: 9570550
    Abstract: A method for forming a semiconductor device comprising forming a stack of nanowires, the stack including a first nanowire having a first length, and a second nanowire having a second length, the second nanowire arranged above the first nanowire, forming a sacrificial gate stack on the stack of nanowires, growing a source/drain region on the first, second nanowires, removing the sacrificial gate stack to expose channel regions of the first and second nanowires, and forming a gate stack over the channel regions.
    Type: Grant
    Filed: January 5, 2016
    Date of Patent: February 14, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, William L. Nicoll, Hanfei Wang
  • Patent number: 9559129
    Abstract: The present invention provides an antenna in that the adhesive intensity of a conductive body formed on a base film is increased, and a semiconductor device including the antenna. The invention further provides a semiconductor device with high reliability that is formed by attaching an element formation layer and an antenna, wherein the element formation layer is not damaged due to a structure of the antenna. The semiconductor device includes the element formation layer provided over a substrate and the antenna provided over the element formation layer. The element formation layer and the antenna are electrically connected. The antenna has a base film and a conductive body, wherein at least a part of the conductive body is embedded in the base film. As a method for embedding the conductive body in the base film, a depression is formed in the base film and the conductive body is formed therein.
    Type: Grant
    Filed: May 10, 2012
    Date of Patent: January 31, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Kyosuke Ito, Junya Maruyama, Takuya Tsurume, Shunpei Yamazaki
  • Patent number: 9559181
    Abstract: The present disclosure provides a semiconductor device that includes a substrate of a first semiconductor material; a fin feature having a first portion, a second portion and a third portion stacked on the substrate; an isolation feature formed on the substrate and disposed on sides of the fin feature; semiconductor oxide features including a second semiconductor material, disposed on recessed sidewalls of the second portion, defining dented voids overlying the semiconductor oxide features and underlying the third portion; and a gate stack disposed on the fin feature and the isolation feature. The gate stack includes a gate dielectric layer extended into and filling in the dented voids. The first and third portions include the first semiconductor material having a first lattice constant. The second portion includes the second semiconductor material having a second lattice constant different from the first lattice constant.
    Type: Grant
    Filed: November 26, 2013
    Date of Patent: January 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Carlos H. Diaz
  • Patent number: 9553054
    Abstract: Strain detection structures used with bonded wafers and chips and methods of manufacture are disclosed. The method includes forming lower metal wiring structures associated with a lower wafer structure. The method further includes bonding the lower wafer structure to an upper wafer structure and thinning the upper wafer, and forming upper metal wiring structures. The method further includes electrically linking the lower metal wiring structures to the upper metal wiring structures by formation of through silicon via structures to form an electrically connected chain extending between multiple wafer structures. The method further includes forming contacts to an outside environment which electrically contact two of the lower metal wiring structures.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: January 24, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Mukta G. Farooq, John A. Fitzsimmons, Erdem Kaltalioglu, Wei Lin, Spyridon Skordas, Kevin R. Winstel
  • Patent number: 9548364
    Abstract: This application relates to graphene based heterostructures and methods of making graphene based heterostructures. The graphene heterostructures comprise: i) a first encapsulation layer; ii) a second encapsulation layer; and iii) a graphene layer. The heterostructures find application in electronic devices.
    Type: Grant
    Filed: March 22, 2012
    Date of Patent: January 17, 2017
    Assignee: The University of Manchester
    Inventors: Andre Geim, Kostya Novoselov, Roman Gorbachev, Leonid Ponomarenko
  • Patent number: 9543450
    Abstract: Semiconductor devices and methods for manufacturing the same are provided. In one embodiment, the method may include: forming a first shielding layer on a substrate, and forming one of source and drain regions with the first shielding layer as a mask; forming a second shielding layer on the substrate, and forming the other of the source and drain regions with the second shielding layer as a mask; removing a portion of the second shielding layer which is next to the other of the source and drain regions; forming a first gate dielectric layer and floating gate layer; forming a mask layer as a spacer on a sidewall of a remaining portion of the second shielding layer, and patterning the floating gate layer with the mask layer as a mask, and then removing the mask layer; and forming a second gate dielectric layer, and forming a gate conductor as a spacer on the sidewall of the remaining portion of the second shielding layer.
    Type: Grant
    Filed: December 4, 2012
    Date of Patent: January 10, 2017
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventor: Huilong Zhu
  • Patent number: 9543391
    Abstract: According to example embodiments a transistor includes a channel layer on a substrate, a first channel supply layer on the channel, a depletion layer, a second channel supply layer, source and drain electrodes on the first channel supply layer, and a gate electrode on the depletion layer. The channel includes a 2DEG channel configured to generate a two-dimensional electron gas and a depletion area. The first channel supply layer corresponds to the 2DEG channel and defines an opening that exposes the depletion area. The depletion layer is on the depletion area of the channel layer. The second channel supply layer is between the depletion layer and the depletion area.
    Type: Grant
    Filed: June 14, 2012
    Date of Patent: January 10, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: In-jun Hwang, Jae-joon Oh, Jae-won Lee, Hyo-ji Choi
  • Patent number: 9543346
    Abstract: An imaging element according to the present disclosure includes: a first pixel and a second pixel each including a light receiving section and a light condensing section, in which the light receiving section includes a photoelectric conversion element, and the light condensing section is configured to allow entering light to be condensed toward the light receiving section; a trench provided between the first pixel and the second pixel; a first light shielding film embedded in the trench; and a second light shielding film provided on part of a light receiving surface of the light receiving section of the second pixel, in which the second light shielding film is continuous with the first light shielding film.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: January 10, 2017
    Assignee: Sony Corporation
    Inventor: Hirotoshi Nomura
  • Patent number: 9543194
    Abstract: In one embodiment, a semiconductor device includes a first insulator, and conductors and second insulators alternately provided on the first insulator. Each second insulator of the second insulators has a first side face adjacent to one of the conductors via a first air gap, a second side face adjacent to one of the conductors via a second air gap, first lower faces in contact with the first insulator, and second lower faces provided above the first insulator via third air gaps.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: January 10, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Kiyomitsu Yoshida
  • Patent number: 9528665
    Abstract: A method for fabricating light-emitting devices includes obtaining a plurality of light-emitting diode (LED) chips fabricated to emit blue light and preparing a phosphor-containing material comprising a matrix material having dispersed therein a mixture of a red phosphor and a green phosphor in a fixed ratio to each other. The method also includes disposing different thicknesses of the phosphor-containing material on different ones of the LED chips. The fixed ratio is chosen such that LED chips having different thicknesses of the phosphor-containing material emit light characterized by different points along the Planckian locus in a CIE chromaticity diagram.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: December 27, 2016
    Assignee: LedEngin, Inc.
    Inventors: Zequn Mei, Truc Phoung Thi Vu
  • Patent number: 9524994
    Abstract: An image sensor with an array of pixels is provided. In order to achieve high image quality, it may be desirable to improve well capacity of individual pixels within the array. When forming each pixel, multiple n-type compartments having p-type isolation regions interposed between compartments may be formed. These compartments may have higher dopant concentrations due to lateral depletion that may occur within multiple PN-NP back to back junctions to assist full depletion at pinning-voltage. Compartments may allow distributing a moderately higher electric-field over a larger portion of the photodiode while lowering peak electric-fields that contribute to dark-current. Compartments will thereby improve the well capacity of the photodiode while preventing additional noise that may degrade the quality of the image signal. The quantity, doping, and depth of these compartments may be selected to maximize well capacity while minimizing effects on operating voltage, manufacturing cost, and power consumption.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: December 20, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventor: Raminda Madurawe
  • Patent number: 9525024
    Abstract: An embodiment is a method comprising diffusing carbon through a surface of a substrate, implanting carbon through the surface of the substrate, and annealing the substrate after the diffusing the carbon and implanting the carbon through the surface of the substrate. The substrate comprises a first gate, a gate spacer, an etch stop layer, and an inter-layer dielectric. The first gate is over a semiconductor substrate. The gate spacer is along a sidewall of the first gate. The etch stop layer is on a surface of the gate spacer and over a surface of the semiconductor substrate. The inter-layer dielectric is over the etch stop layer. The surface of the substrate comprises a surface of the inter-layer dielectric.
    Type: Grant
    Filed: July 21, 2015
    Date of Patent: December 20, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chen Su, Huang-Ming Chen, Chun-Feng Nieh, Pei-Chao Su
  • Patent number: 9523895
    Abstract: An embodiment of the invention relates to a TFT-LCD array substrate comprising a substrate, a gate line and a data line formed on the substrate, a pixel electrode and a thin film transistor formed in a pixel region defined by the gate line and the data line, wherein the thin film transistor comprises a gate electrode, a source electrode, and a transparent drain electrode, and the transparent drain electrode is electrically connected with the pixel electrode.
    Type: Grant
    Filed: April 14, 2014
    Date of Patent: December 20, 2016
    Assignees: BEIJING BOE OPTOELECTRONICS TECHNOLOGY CO., LTD., BOE TECHNOLOGY GROUP CO., LTD.
    Inventors: Wei Li, Jeong Hun Rhee
  • Patent number: 9520378
    Abstract: A thermal matched composite material, suitable for use as a die is described. In one example, the material includes a metal plate and a substrate having a coefficient of thermal expansion (CTE) lower than the metal plate to carry microelectronic circuits. An adhesive layer between the substrate and the metal plate physically attaches the metal plate to the substrate so that the combined metal plate and substrate have a higher CTE than the substrate alone.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: December 13, 2016
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Shawna M. Liff
  • Patent number: 9520434
    Abstract: An image pickup module includes: an image pickup chip including a main surface on which a light-receiving portion of an image pickup device and a plurality of electrodes connected to the light-receiving portion are formed; and a wiring board including flying leads bonded to the respective plurality of electrodes.
    Type: Grant
    Filed: October 2, 2014
    Date of Patent: December 13, 2016
    Assignee: OLYMPUS CORPORATION
    Inventor: Masashi Yamada