Patents Examined by Jesse Y Miyoshi
  • Patent number: 9917647
    Abstract: A combination underfill-dam and electrical-interconnect structure for an opto-electronic engine. The structure includes a first plurality of electrical-interconnect solder bodies. The first plurality of electrical-interconnect solder bodies includes a plurality of electrical interconnects. The first plurality of electrical-interconnect solder bodies, is disposed to inhibit intrusion of underfill material into an optical pathway of an opto-electronic component for the opto-electronic engine. A system and an opto-electronic engine that include the combination underfill-dam and electrical interconnect structure are also provided.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: March 13, 2018
    Assignee: Hewlett Packard Enterprise Development LP
    Inventors: Sagi Varghese Mathai, Michael Renne Ty Tan, Paul Kessler Rosenberg, Wayne Victor Sorin, Georgios Panotopoulos, Susant K. Patra, Joseph Straznicky
  • Patent number: 9917145
    Abstract: A light-emitting device includes a drive transistor for controlling the quantity of current supplied to a light-emitting element, a capacitor element electrically connected to a gate electrode of the drive transistor, and an electrical continuity portion for electrically connecting the drive transistor and the light-emitting element, these elements being disposed on a substrate. The electrical continuity portion is disposed on the side opposite to the capacitor element with the drive transistor disposed therebetween.
    Type: Grant
    Filed: May 27, 2016
    Date of Patent: March 13, 2018
    Assignee: SEIKO EPSON CORPORATION
    Inventors: Takehiko Kubota, Eiji Kanda, Ryoichi Nozawa
  • Patent number: 9905476
    Abstract: Multiple gate stack portions are formed in a gate cavity by direct metal gate patterning to provide FinFETs having different threshold voltages. The different threshold voltages are obtained by selectively incorporating metal layers with different work functions in different gate stack portions.
    Type: Grant
    Filed: January 23, 2017
    Date of Patent: February 27, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Ruqiang Bao, Siddarth A. Krishnan, Unoh Kwon, Keith Kwong Hon Wong
  • Patent number: 9905557
    Abstract: A connection electrode for connecting a transistor including a semiconductor material other than an oxide semiconductor to a transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode.
    Type: Grant
    Filed: July 29, 2014
    Date of Patent: February 27, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Saito, Kiyoshi Kato, Atsuo Isobe
  • Patent number: 9899382
    Abstract: A FinFET device structure is provided. The FinFET device structure includes a fin structure formed over a substrate and an isolation structure formed over the substrate. The FinFET device structure includes a first gate structure and a second gate structure formed over the fin structure. The first gate structure has a first top width in a direction that is parallel to the fin structure, the second gate structure has a second top width in a direction that is parallel to the fin structure, and the first top width is greater than the second top width.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Ching Huang, Tsung-Yu Chiang, Ya-Wen Yang
  • Patent number: 9893026
    Abstract: Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: February 13, 2018
    Assignee: Elwha LLC
    Inventors: William David Duncan, Roderick A. Hyde, Jordin T. Kare, Thomas M. McWilliams, Thomas Allan Weaver, Lowell L. Wood, Jr.
  • Patent number: 9887388
    Abstract: A light emitting element includes an anode, a light transmitting cathode, and a light emitting layer sandwiched therebetween, formed on a surface of a substrate. Light emitted by the light emitting layer by voltage being applied between the electrodes is output from a surface toward the side of the light transmitting electrode. A light scattering layer for scattering evanescent light generated at the surface is provided on the surface of the light transmitting electrode. The light scattering layer has a first scattering portion having an uneven structure and a lower refractive index than the light emitting layer, and second scattering portions that fill at least the bottoms of recesses of the uneven structure and has a different refractive index from the first scattering portion. The distance between the bottoms of the recesses and the surface of the light transmitting electrode is a seepage depth of the evanescent light or less.
    Type: Grant
    Filed: October 15, 2009
    Date of Patent: February 6, 2018
    Assignee: UDC Ireland Limited
    Inventor: Masayuki Naya
  • Patent number: 9887177
    Abstract: Inter-substrate coupling and alignment using liquid droplets can include electrical and plasmon modalities. For example, a set of droplets can be placed on a bottom substrate. A top substrate can be placed upon the droplets, which uses the droplets to align the substrates. Using the droplets in a capacitive or plasmon coupling modality, information or power can be transferred between the substrates using the droplets.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: February 6, 2018
    Assignee: Elwha LLC
    Inventors: William David Duncan, Roderick A. Hyde, Jordin T. Kare, Thomas M. McWilliams, Thomas Allan Weaver, Lowell L. Wood, Jr.
  • Patent number: 9887385
    Abstract: An organic light emitting diode display device and a method for manufacturing the same are disclosed where permeation of moisture and oxygen may be prevented. The organic light emitting diode display device includes a protective members including an first inorganic film formed on a substrate to completely cover an organic light emitting diode, an organic film formed on the first inorganic film, and a second inorganic film formed on the first inorganic film and the organic film, wherein the organic film includes a first organic pattern corresponding to upper and side parts of the organic light emitting diode, and at least one second organic pattern being spaced from the first organic pattern and surrounding the first organic pattern, and the second organic pattern has an upper surface having the same height as an upper surface of the first organic pattern.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: February 6, 2018
    Assignee: LG Display Co., Ltd.
    Inventors: Yun-Ho Kook, Tae-Joon Song, Yong-Hee Han
  • Patent number: 9883271
    Abstract: A wireless headset supports simultaneous connections to two or more audio sources and can concurrently output audio from the different sources. The audio may include voice and/or audio playback, e.g., music playback. The wireless headset includes a first transceiver configured to receive a first audio input from a first source, a second transceiver configured to receive a second audio input from a second source, and an audio mixer configured to combine the first and second audio inputs into output audio.
    Type: Grant
    Filed: December 12, 2008
    Date of Patent: January 30, 2018
    Assignee: QUALCOMM Incorporated
    Inventor: Kuntal Sampat
  • Patent number: 9876127
    Abstract: A backside-illuminated photodetector structure comprising a first reflecting region, a second reflecting region and a semiconductor region. The semiconductor region is between the first reflecting region and the second reflecting region. The semiconductor region comprises a first doped region and a second doped region.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wan-Yu Lee, Ying-Hao Kuo
  • Patent number: 9871171
    Abstract: A light-emitting device comprises a light-emitting structure capable of emitting a light; an electrode formed on a side of the light-emitting structure; a transparent structure formed on a second side of the light-emitting structure, wherein the transparent structure is aligned to a region of the electrode, and comprises a first transparent layer and a second transparent layer around the first transparent layer; a contact structure formed on the second side of the light-emitting structure; and a reflective layer covering the transparent structure and the contact structure.
    Type: Grant
    Filed: November 7, 2014
    Date of Patent: January 16, 2018
    Assignee: EPISTAR CORPORATION
    Inventors: Jen-Li Hu, Tzu-Chieh Hsu
  • Patent number: 9865683
    Abstract: An electronic device includes a semiconductor memory unit that includes: a gate including at least a portion buried in a substrate; a junction portion formed in the substrate on both sides of the gate; and a memory element coupled with the junction portion on one side of the gate, wherein the junction portion includes: a recess having a bottom surface protruded in a pyramid shape; an impurity region formed in the substrate and under the recess; and a contact pad formed in the recess.
    Type: Grant
    Filed: January 2, 2015
    Date of Patent: January 9, 2018
    Assignee: SK hynix Inc.
    Inventor: Hyung-Suk Lee
  • Patent number: 9865731
    Abstract: A semiconductor device includes a p-type metal oxide semiconductor device (PMOS) and an n-type metal oxide semiconductor device (NMOS) disposed over a substrate. The PMOS has a first gate structure located on the substrate, a carbon doped n-type well disposed under the first gate structure, a first channel region disposed in the carbon doped n-type well, and activated first source/drain regions disposed on opposite sides of the first channel region. The NMOS has a second gate structure located on the substrate, a carbon doped p-type well disposed under the second gate structure, a second channel region disposed in the carbon doped p-type well, and activated second source/drain regions disposed on opposite sides of the second channel region.
    Type: Grant
    Filed: November 15, 2013
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: I-Chih Chen, Ying-Lang Wang, Chih-Mu Huang, Ying-Hao Chen, Wen-Chang Kuo, Jung-Chi Jeng
  • Patent number: 9865523
    Abstract: Methods and apparatus entailing an interconnect structure comprising interconnect features disposed in dielectric material over a substrate. Each interconnect feature comprises an interconnect member and a via extending between the interconnect member and a conductive member formed within the dielectric material. A through-silicon-via (TSV) structure is formed laterally offset from the interconnect structure by forming a first portion of the TSV structure with a first conductive material and forming a second portion of the TSV structure with a second conductive material. Forming the second portion of the TSV structure occurs substantially simultaneously with forming one of the interconnect features.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: January 9, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chi Lin, Tsang-Jiuh Wu, Wen-Chih Chiou
  • Patent number: 9859259
    Abstract: The present invention provides a light emitting apparatus comprising a three-color light emitting device unit including at least three light emitting diode (LED) chips for respectively emitting red, green and blue light; a white light emitting device unit including at least one blue LED chip with a fluorescent substance formed thereon; and a substrate provided with a first electrode connected in common to ends of the LED chips and second electrodes formed to correspond respectively to the LED chips.
    Type: Grant
    Filed: March 8, 2006
    Date of Patent: January 2, 2018
    Assignee: Seoul Semiconductor Co., Ltd.
    Inventor: Jae Hong Lee
  • Patent number: 9853032
    Abstract: A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: December 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: JungWoo Seo
  • Patent number: 9847404
    Abstract: This improved, fluctuation resistant FinFET, with a doped core and lightly doped epitaxial channel region between that core and the gate structure, is confined to the active-gate span because it is based on a channel structure having a limited extent. The improved structure is capable of reducing FinFET random doping fluctuations when doping is used to control threshold voltage, and the channel structure reduces fluctuations attributable to doping-related variations in effective channel length. Further, the transistor design affords better source and drain conductance when compared to prior art FinFETs. Two representative embodiments of the key structure are described in detail.
    Type: Grant
    Filed: September 11, 2013
    Date of Patent: December 19, 2017
    Assignees: SemiWise Limited, Semi Solutions LLC
    Inventors: Robert J. Strain, Asen Asenov
  • Patent number: 9847429
    Abstract: A semiconductor device is provided with a first oxide semiconductor film over an insulating surface; a second oxide semiconductor film over the first oxide semiconductor film; a third oxide semiconductor film in contact with a top surface of the insulating surface, a side surface of the first oxide semiconductor film, and side and top surfaces of the second oxide semiconductor film; a gate insulating film over the third oxide semiconductor film; and a gate electrode in contact with the gate insulating film and faces the top and side surfaces a of the second oxide semiconductor film. A thickness of the first oxide semiconductor film is larger than a sum of a thickness of the third oxide semiconductor film and a thickness of the gate insulating film, and the difference is larger than or equal to 20 nm.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: December 19, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Daisuke Matsubayashi, Yoshiyuki Kobayashi
  • Patent number: 9847302
    Abstract: Hydroxyl moieties are formed on a surface over a semiconductor substrate. The surfaces are silylized to replace the hydroxyl groups with silyl ether groups, the silyl ether groups being of the form: —OSiR1R2R3, where R1, R2, and R3 are each hydrocarbyl groups comprising at least one carbon atom. Silylation protects the wafers from forming defects through hydrolysis while the wafers are being transported or stored under ambient conditions.
    Type: Grant
    Filed: August 23, 2013
    Date of Patent: December 19, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsiao-Chen Wu, Fang Lin