Patents Examined by Jhihan B Clark
  • Patent number: 6627991
    Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.
    Type: Grant
    Filed: April 10, 2000
    Date of Patent: September 30, 2003
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Rajeev Joshi
  • Patent number: 6603209
    Abstract: The present invention provides a method for fabricating a compliant microelectronic device package and an associated apparatus for substantially obviating thermal, compliancy and interconnection problems. Flexible, dielectric layers are used having on a first surface a plurality conductive leads which are each electrically coupled at a first end to at least one conductive pad also coupled to the first surface of the dielectric layers. A second end of the conductive leads are further coupled between the dielectric layers across a bonding gap. A compliant layer is then coupled to the bottom surface of the dielectric layers. One of the dielectric layers is coupled to the surface of a die by one of the compliant layer such that the die bond pads are juxtaposed with respective leads in the bonding gap. This assembly is attached to a protective structure and is encapsulated. A solder mask may be placed over the exposed surface of the dielectric layers to cover the leads and prevent shoring.
    Type: Grant
    Filed: May 6, 1999
    Date of Patent: August 5, 2003
    Assignee: Tessera, Inc.
    Inventors: Thomas H. DiStefano, Konstantine Karavakis, Craig Mitchell, John W. Smith
  • Patent number: 6525410
    Abstract: A semiconductor device comprising an integrated circuit and an information unit, said unit being electrically separate from said integrated circuit; an integrated antenna electrically connected with said unit; and an electronic data bank integral with said unit. A method of fabricating an information unit into an integrated circuit chip comprising forming an integrated circuit into a semiconductor substrate using a plurality of process steps; concurrently forming an information unit using a selection of said process steps so that said unit becomes integrated into said chip but remains electrically separate from said integrated circuit; concurrently forming an antenna using a selection of said process steps so that said antenna becomes integrated into said chip and electrically connected to said information unit; providing a data bank within said information unit; and encoding electronic data permanently into said data bank.
    Type: Grant
    Filed: July 15, 1999
    Date of Patent: February 25, 2003
    Assignee: Texas Instruments Incorporated
    Inventors: Tito Gelsomini, Giulio G. Marotta, Sebastiano D'Arrigo
  • Patent number: 6489678
    Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: December 3, 2002
    Assignee: Fairchild Semiconductor Corporation
    Inventor: Rajeev Joshi
  • Patent number: 6433436
    Abstract: A structure and process to define a via/interconnect structure is described. The structure is formed by reactive ion etching (RIE) where vias are formed first then the interconnects. The disclosed method relies on first depositing a metal with a thickness equivalent to the total height of the via and interconnect. Once vias are delineated by forming a hard mask and lithography, the lines are patterned using a lithographic step. Vias and lines are formed using lithography and RIE in one step and interfacial integrity is maintained resulting in high electromigration performance.
    Type: Grant
    Filed: May 26, 1999
    Date of Patent: August 13, 2002
    Assignee: International Business Machines Corporation
    Inventors: Christopher Adam Feild, Roy Charles Iggulden, Rajiv Vasant Joshi, Edward William Kiewra
  • Patent number: 6426548
    Abstract: A semiconductor device, comprising: a semiconductor chip having on its main plane a plurality of external electrodes each having a joining portion; an insulating substrate having a predetermined pattern of leads thereon and having no device hole for said semiconductor chip, each of said leads being provided with an inner lead having a joining portion which is joined through solder to a corresponding one of the joining portions of said external electrodes of said semiconductor chip to provide a joined portion; and a molding resin for sealing said joined portion including the solder, wherein the joining portion of the external electrode comprises a metal selected from the group consisting of gold and tin, the joining portion of the inner lead comprises a metal selected from the group consisting of gold and tin, provided that, when the metal constituting the joining portion of the external electrode is gold, the metal constituting the joining portion of the inner lead is tin, or vice versa, and the solder compri
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: July 30, 2002
    Assignee: Hitachi Cable Ltd.
    Inventors: Mamoru Mita, Gen Murakami
  • Patent number: 6424034
    Abstract: A method and apparatus for packaging microprocessors and memory devices on a single silicon substrate is described. Microprocessors and memory devices are placed on both sides of the silicon substrate. Through holes are formed in the substrate to connect the microprocessor and memory devices together. By packaging the microprocessor and memory element this way, the propagation length between the memory and the microprocessors is shortened, and timing skews are minimized, and data transmission speed is increased. In addition, additional active and passive circuits and/or components can also be fabricated in one or both sides of the silicon substrate.
    Type: Grant
    Filed: August 31, 1998
    Date of Patent: July 23, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes, Paul Farrar
  • Patent number: 6424030
    Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.
    Type: Grant
    Filed: May 24, 2001
    Date of Patent: July 23, 2002
    Assignees: Hitachi, Ltd., Hitachi Tobu Semiconductor, Ltd., Akita Electronics Co., Ltd.
    Inventors: Watanabe Masayuki, Sugano Toshio, Tsukui Seiichiro, Ono Takashi, Wakashima Yoshiaki
  • Patent number: 6407446
    Abstract: An aspect of the present invention provides a semiconductor chip package that can accommodate many outer leads in a relatively small package outline. The package includes a package body and outer leads along the outline of the package body. The package body outline has concave portions to increase the number of outer leads without increasing the package footprint. For example, the package can have a QFP outline with concave portions on the sides of the QFP outline. The package can have an SOP outline with concave portions on two opposite sides of the SOP outline.
    Type: Grant
    Filed: December 28, 2000
    Date of Patent: June 18, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je Bong Kang, Jae Won Lee, Heui Seog Kim
  • Patent number: 6404043
    Abstract: A chip stack comprising at least two base layers, each of which includes a base substrate and a first conductive pattern disposed on the base substrate. The chip stack further comprises at least one interconnect frame having a second conductive pattern disposed thereon. The interconnect frame is disposed between the base layers, with the second conductive pattern being electrically connected to the first conductive pattern of each of the base layers. Also included in the chip stack are at least two integrated circuit chips which are electrically connected to respective ones of the first conductive patterns. One of the integrated circuit chips is at least partially circumvented by the interconnect frame and at least partially covered by one of the base layers. The chip stack further comprises a transposer layer comprising a transposer substrate having a third conductive pattern disposed thereon.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: June 11, 2002
    Assignee: Dense-Pac Microsystems, Inc.
    Inventor: Harlan R. Isaak
  • Patent number: 6404041
    Abstract: The power switch has considerably reduced common-mode interference and relatively reduced circuit complexity. The power switch is formed of a semiconductor chip on a leadframe. A first terminal of the semiconductor chip is connected to the active potential and a second terminal for inactive potential is connected to the leadframe. The second terminal is either the drain of a transistor or the anode of a diode.
    Type: Grant
    Filed: October 18, 1999
    Date of Patent: June 11, 2002
    Assignee: Infineon Technologies AG
    Inventors: Josef-Matthias Gantioler, Frank Klotz, Martin März, Helmut Gassel
  • Patent number: 6404057
    Abstract: Ta—Al—N is formed on a semiconductor device structure, such as a wiring line, to prevent interdiffusion between surrounding layers. The Ta—Al—N material serves as a diffusion between (i) two conductor layers, (ii) a semiconductor layer and a conductor layer, (iii) an insulator layer and a conductor layer, (iv) an insulator layer and a semiconductor layer, or (v) two semiconductor layers. Another use is to promote adhesion of adjacent layers, such as between (i) two conductor layers, (ii) a conductor layer and an insulator layer, (iii) a semiconductor layer and a conductor layer, or (iv) two semiconductor layers. The Ta—Al—N material also is used to form a contact or electrode. The Ta—Al—N material includes between 0.5% and 99.0% aluminum, between 0.5% and 99.0% tantalum, and between 0.5% and 99.0% nitrogen.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: June 11, 2002
    Assignee: Micron Technology, Inc.
    Inventors: Salman Akram, Scott G. Meikle
  • Patent number: 6400025
    Abstract: The crude Ti particles prepared by molten salt electrolysis or Iodide method are classified into each particle diameter according to contents of impurities, and the crude Ti particles having a desired particle diameter are selected from the crude Ti particles classified depending on each particle diameter. Otherwise, the crude Ti particles are acid-treated. Then they are electron-beam-melted. Through the above production process, there is prepared a highly purified Ti material having an oxygen content of not more than 350 ppm, Fe, Ni and Cr contents of not more than 15 ppm each, Na and K contents of not more than 0.5 ppm each, a reduction of area as a material characteristic of not less than 70%, and a thermal conductivity of not less than 16 W/m K. In short, the highly purified Ti material satisfying high purity, good processability and good thermal conductivity can be obtained.
    Type: Grant
    Filed: March 29, 1999
    Date of Patent: June 4, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Takashi Ishigami, Mituo Kawai, Noriaki Yagi
  • Patent number: 6396148
    Abstract: Chips first packaging structures and methods of fabrication are presented which employ electroless metallizations. An electroless barrier metal is disposed over and in electrical contact with at least one aluminum contact pad of the chips first integrated circuit. The electroless barrier metal is a first electroless metal and is a different material than the at least one aluminum contact pad. An electroless interconnect metal is disposed above and electrically contacts the electroless barrier metal. The electroless interconnect metal is a second electroless metal, which is different from the first electroless metal. As an example, the electroless barrier metal comprises electroless nickel and the electroless interconnect metal comprises electroless copper.
    Type: Grant
    Filed: February 10, 2000
    Date of Patent: May 28, 2002
    Assignee: EPIC Technologies, Inc.
    Inventors: Charles W. Eichelberger, James E. Kohl, Michael E. Rickley
  • Patent number: 6396157
    Abstract: A semiconductor integrated circuit device in accordance with the present invention is provided with first electrode pads, a first insulation layer and a second insulation layer. The first electrode pad are formed on the circuit formation face side of an IC chip. The first insulation layer is placed on areas other than the upper portions of the first electrode pads. The second insulation layer, which is made from a photosensitive material, is formed on the first insulation layer with an opening section for allowing at least one portion of the first electrode, the wire and at least one portion of the second electrode to be exposed. Here, the wire and the second electrode are formed by filling the opening section of the second insulation layer with particles of a conductive material.
    Type: Grant
    Filed: January 3, 2001
    Date of Patent: May 28, 2002
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Hiroyuki Nakanishi, Katsunobu Mori, Toshiya Ishio, Shinji Suminoe
  • Patent number: 6388332
    Abstract: An integrated circuit includes a plurality of blocks of cells, and a plurality of layers with conductors for signal and power routing. Power and ground connections for individual cells are supplied by power and ground conductors in a first layer of conductors at the cell level. Power and ground conductors at the block level are supplied by power and ground conductors at the top level of the layers which are connected to the first layer power and ground conductors by stacked vias. Intervening layers of conductors can be used for signal routing. This routing technique improves circuit density as compared to prior techniques where the block level power and ground conductors were in a second, lower level of conductors instead of a top level. A layout method is also disclosed in which the conductors for signal routing are defined in dependence on the placement of the block level power and ground conductors.
    Type: Grant
    Filed: August 10, 1999
    Date of Patent: May 14, 2002
    Assignee: Philips Electronics North America Corporation
    Inventors: Lily Aggarwal, Linda Ann Barnhart
  • Patent number: 6388329
    Abstract: A high melting point metal wiring layer, a second aluminum wiring layer, and a third aluminum wiring layer are stacked on transistors forming an inverter train of a hierarchical power supply structure respectively. The high melting point metal wiring layer is employed as a local wire for connecting the transistors with each other, the second aluminum wiring layer is employed as a local bus wire and a hierarchical power supply wire, and the third aluminum wiring layer is employed as a main bus wire and a power supply wire to intersect with the respective wires. Consequently, the wiring layers are easy to lay out, while no main bus region is required dissimilarly to the prior art and it is possible to reduce the layout area.
    Type: Grant
    Filed: November 6, 2000
    Date of Patent: May 14, 2002
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Shigehiro Kuge, Kazutami Arimoto
  • Patent number: 6384471
    Abstract: The present invention concerns a package for an integrated circuit (3) of the type comprising a cavity (2) in which the integrated circuit (3) is mounted, the active surface (10) of the integrated circuit (3) being electrically connected to the package on the level of connection (Nc) of an array of balls (13i) to the package, providing a mechanical and electrical link between the integrated circuit (3) and a printed circuit card to which the package must be assembled. It is characterized in that it comprises an additional layer (14) that is rigid and electrically neutral, mounted on the level of connection (Nc) of the integrated circuit (3) and the balls (13i) and containing the balls (13i). It particularly applies to the connections of BGA and PBGA packages.
    Type: Grant
    Filed: January 4, 2001
    Date of Patent: May 7, 2002
    Assignee: Bull S.A.
    Inventors: Claude Petit, Yves Stricot
  • Patent number: 6384487
    Abstract: A bow resistant semiconductor package includes a semiconductor die, a leadframe and a plastic body. The plastic body includes a molded inner member encapsulating the die, and a molded outer member encapsulating the molded inner member. The inner member rigidities the package, and is dimensioned such that the outer member has substantially equal volumes of molding compound on either side of the leadframe. The equal volumes of molding compound reduce thermo-mechanical stresses generated during cooling of the molding compound, and reduce package bow. With reduced package bow, a planarity of the terminal leads on the package is maintained. Also, stresses on bonded connections between the terminal leads and electrodes on a supporting substrate, such as a printed circuit board or multi chip module substrate are reduced.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: May 7, 2002
    Assignee: Micron Technology, Inc.
    Inventor: Steven R. Smith
  • Patent number: 6384475
    Abstract: A component for making microelectronic units includes a grid of interspersed leads with ends of the various leads being connected to one another by frangible elements. One end of each lead is bonded to a top element and the other end of each lead is bonded to a bottom element. The top and bottom elements are moved away from one another, thereby breaking the frangible elements and deforming the leads towards a vertically extensive disposition. A flowable composition such as dielectric material may be injected around the leads during or after the moving step. The resulting unit may be used to form permanent or temporary connections between microelectronic elements.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: May 7, 2002
    Assignee: Tessera, Inc.
    Inventors: Masud Beroz, Belgacem Haba, Christopher M. Pickett