Abstract: An interconnect structure for use in semiconductor devices, comprising: (a) a thin and elongated aluminum wire connected to a first metal structure; and (b) a plurality of regularly spaced dummy tungsten plugs which are connected to the aluminum wire at one end and are buried in an underlying dielectric layer so that it is insulated at the other end. The dummy tungsten plugs absorb the mobile aluminum atoms generated through stress-induced migration when the interconnect structure is subject to a rapid temperature change, thus preventing the via bulging problem which could seriously damage the second metal structure above the first metal structure.

Abstract: A package is disclosed in which deterioration of insulating encapsulation resin attributable to the generation of heat at source wires caused by an increase in a drain current is prevented. Specifically, there is provided a semiconductor package including a header made of metal, a semiconductor chip forming a power MOSFET secured on the header, an encapsulation element made of insulating resin covering the semiconductor chip, header and the like, a suspended lead contiguous with the header protruding from one side surface of the encapsulation element, a source lead and a gate lead protruding in parallel from one side surface of the encapsulation element, and wires positioned in the encapsulation element for connecting electrodes on the upper surface of the semiconductor chip and the source and gate leads. The source lead is constituted by a plurality of leads in parallel with each other, and the ends of the leads are coupled into one coupling portion in the encapsulation element.

Abstract: A structure including a conductive, preferably metallic conductive layer is provided with leads on a bottom surface. The leads have fixed ends permanently attached to the structure and free ends detachable from the structure. The structure is engaged with a microelectronic element such as a semiconductor chip or wafer, the free ends of the leads are bonded to the microelectronic element, and the leads are bent by moving the structure relative to the microelectronic element. Portions of the conductive layer are removed, leaving residual portions of the conductive layer as separate electrical terminals connected to at least some of the leads. The conductive layer mechanically stabilizes the structure before bonding, and facilitates precise registration of the leads with the microelectronic element. After the conductive layer is converted to separate terminals, it does not impair free movement of the terminals relative to the microelectronic element.

Abstract: For an integrated semiconductor chip to operate reliably, it is necessary to homogenize a substrate potential as far as possible in all regions of the chip. In order to improve the substrate contact-connections on the chip, modular dummy structures are configured in such a way that, in addition to homogenizing the areal occupancy of the chip, they form extensive electrically conductive contact between the substrate and metal interconnects of a metallization plane of the chip. This achieves homogenization of the substrate potential and improvement of the wave guiding properties of wiring planes lying above the dummy structures without an additional process step or an additional chip area being required for this purpose.

Abstract: A conductor path contacting arrangement for contacting a first conductor path, which is applied on a substrate and covered with a first insulating layer, via a contact hole in the first insulating layer to a second conductor path. The contact hole overlies a region above the first conductor and a region, adjacent thereto, above the substrate; and inside the contact hole the second conductor path is stepped down from the contact region having the first conductor path toward the substrate therebeneath. This allows better control of the contact hole junction resistance.

Abstract: A lead frame and method of making the same are provided. The lead frame includes a die mounting portion, first and second pairs of tie bars, and first and second tie bar bridges extending between respective second extension portions of each tie bar pair. First and second pairs of tie bars are mechanically coupled to respective first and second ends of the die mounting portion. Each of the tie bars includes a first extension portion, a second extension portion, a tie bar span mechanically coupled to the first end of the die mounting portion via the first extension portion, a tie bar flap formed along a longitudinal reinforcement crease, and a lateral reinforcement portion extending from said first extension portion to said die mounting portion. The tie bar flap and the tie bar span lie in intersecting planes and are connected along the longitudinal reinforcement crease between the first extension portion and the second extension portion.

Abstract: An electronic package and contacts therefor are disclosed. The package includes a planar base and a plurality of conductive pads positioned on one planar side of the base. Each contact is formed as a generally unitary body from a conductive material, and is conductively coupled to a respective one of the pads. Each contact has a coupling tab and a longitudinally extending blade coupled to the tab. The tab extends along the respective pad and is coupled thereto. The blade extends perpendicularly with respect to the one planar side of the base.

Abstract: A semiconductor package, and a method for fabricating the package are provided. The package includes a plastic body, and a pair of stacked semiconductor dice encapsulated in the plastic body, and wire bonded to separate leadframe segments. A first leadframe segment includes lead fingers configured to support a first semiconductor die of the stacked pair, and to form terminal leads of the package. A second leadframe segment is attached to the first leadframe segment, and includes lead fingers that support a second semiconductor die of the stacked pair. The lead fingers of the second leadframe are in physical and electrical contact with the leadfingers of the first leadframe. In addition, tip portions of the lead fingers of the first leadframe segment are staggered relative to tip portions of the lead fingers of the second leadframe segment to provide space for bond wires.

Abstract: A small size electronic part comprises a silicon substrate having a functional element and a signal output portion to output a signal from the functional element to outside the electronic part; a glass substrate provided on the silicon substrate such that the signal output portion of the silicon substrate is in contact with the glass substrate; a communicating hole provided in the glass substrate and at least a portion of the signal output portion of the silicon substrate so as to pass through the glass substrate and cut into at least a part of the signal output portion; and a conductive film provided on an inner wall surface of the communicating hole and extending on a surface of the glass substrate.

Abstract: A semiconductor device having a semiconductor substrate and a bonding pad portion formed on the semiconductor substrate, the bonding pad portion having: an insulating film formed on the semiconductor substrate and a first-level conductive pad layer of a large island shape formed on the insulating film; first-level to (n−1)-level (n is an integer of 3 or larger) interlayer insulating films formed on and over the insulating film; second-level to n-level conductive pad layers formed on the interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer was formed; a plurality of small diameter first through holes from the first-level to (n−1) level formed through the first-level to (n−1) level interlayer insulating films in areas generally corresponding to an area where the first conductive pad layer; a plurality of first contact plugs filled in the small diameter first through holes from the first-level to (n−1)-level, the first contact plugs

Abstract: In a microwave hybrid integrated circuit a metallized recess (8) is formed on the back or face side of a board (1) of the metallization of which recess serves as a bottom plate (6) of a capacitor (5), a remaining portion (9) of the board (1) under the recess (8) serves as the dielectric of the capacitor (5), and a top plate (7) thereof is situated on the face side of the board (1) and makes part of a topological metallization pattern (2), the remaining portion of the thickness of the board (1) in the recess (8) being of 1 to 400 &mgr;m.

Abstract: A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Abstract: There is herein disclosed a semiconductor device comprising an internal cell area 1 on which various logic circuits are formed, an I/O cell area 3 via which a signal is received/transmitted between a pad for connection to the outside and said internal cell area 1, an external pad area 2a formed outside the I/O cell area 3, and an internal pad area 2b formed between the internal cell area 1 and the I/O cell area 3. Since the internal pad area 2b is disposed not only outside the I/O cell area 3, but also between the I/O cell area 3 and the internal cell area 1, the number of pads for the connection to the outside can be increased more than that of a conventional art, and a large number of pins of a chip can be handled. Moreover, since a pad interval does not have to be narrowed, reliability is improved, and manufacture yield is raised.

Abstract: A package for connecting an integrated circuit to a printed circuit board. The package includes an interconnect having a deflectable cantilever and a solder bump. When the integrated circuit is affixed to the interconnect, the solder bump deflects the cantilever. When the solder bump is heated such that the solder reflows, the cantilever springs toward its non-deflected position and is at least partially absorbed by the reflowing solder.

Abstract: Electrode pads are formed on a surface of a semiconductor chip, a first bumps are provided on lower electrodes provided on the electrode pads, and second bumps are provided outside the first bumps. The semiconductor chip has a side wall on one end side in a stepped shape and the first bumps and the second bumps are provided to extend from the surface to a side surfaces of the stepped portion of the semiconductor chip. Also, outer surfaces of the second bumps are formed to project outside from the side surface of the semiconductor chip.

Abstract: A thin film field effect transistors and manufacturing method for the same are described. The channel region of the transistor is spoiled by an impurity such as oxygen, carbon, nitrogen. The photosensitivity of the channel region is reduced by the spoiling impurity and therefore the transistor is endowed with immunity to illumination incident thereupon which would otherwise impair the normal operation of the transistor. The spoiling impurity is not introduced into transistors which are located in order not to receive light rays.

Abstract: A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which is depleted of fluorine to a predetermined depth.

Abstract: A 16 megabit (224) or greater density single deposition layer metal Dynamic Random Access Memory (DRAM) part is described which allows for a die that fits within an industry-standard 300 ml wide SOJ (Small Outline J-wing) package or a TSOP (Thin, Small Outline Package) with little or no speed loss over previous double metal deposition layered 16 megabit DRAM designs. This is accomplished using a die architecture which allows for a single metal layer signal path, together with the novel use of a lead frame to remove a substantial portion of the power busing from the die, allowing for a smaller, speed-optimized DRAM. The use of a single deposition layer metal results in lower production costs, and shorter production time.

Abstract: An integrated circuit includes a conductive layer adjacent a semiconductor substrate. The conductive layer includes conductive lines having gaps therebetween. A fluoro-silicate glass (FSG) layer is over the patterned conductive layer fills the gaps between conductive lines. Also, an undoped oxide layer is on the FSG layer. Peaks of the FSG layer which overlie the conductive metal lines have been reduced by CMP. Thus, a subsequent conductive layer is substantially protected from exposure to fluorine from the FSG layer.

Abstract: The present invention relates to a conductive plug capacitor and method of making for use in multi-level integrated circuit structures. In one embodiment, a tungsten plug is formed in a window in a dielectric layer and thereafter a cavity is formed in the plug. This cavity in the plug may serve as the lower electrode for the capacitor, with a layer of dielectric deposited in the cavity and a top metal electrode deposited on the dielectric layer. An alternative embodiment makes use of not only the inner cavity surfaces of the cavity in the tungsten plug, but also the outer sidewalls of the tungsten plug. To this end, after formation of the tungsten plug heading the cavity formed therein, a partial etchback of the dielectric layer in which the tungsten plug is formed is effective. The capacitor dielectric is then deposited on the sidewalls, the top surface and the interior of the cavity of the tungsten plug thereby increasing the area and thereby the over capacitance.