Patents Examined by Ji H. Bae
  • Patent number: 11144109
    Abstract: An information processing apparatus comprising a first controller, a second controller provided between the first controller and a storage device, and a main controller that sets a power saving state of the first controller, the second controller and the storage device. The first controller transitions to the power saving state in response to a transition request from the main controller, the second controller transitions to the power saving state in response to the power saving state to which the first controller has transitioned, and the first controller starts restoration processing from the power saving state in response to an interrupt from the main controller and determines, based on whether the second controller is performing power control on the storage device, whether to execute preprocessing which is accompanied by access to the storage device.
    Type: Grant
    Filed: January 23, 2019
    Date of Patent: October 12, 2021
    Assignee: Canon Kabushiki Kaisha
    Inventor: Akihiro Matsumoto
  • Patent number: 11132015
    Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: September 28, 2021
    Assignee: Micron Technology, Inc.
    Inventors: Kenji Asaki, Shuichi Tsukada
  • Patent number: 11119559
    Abstract: There is disclosed a method of controlling the frequency of a clock signal in a processor. The method selects a first clock generator to provide a processor clock signal for executing an application. If a threshold event is detected, a second clock generator is selected. The method reduces the frequency of a clock signal generated by the first clock generator while a processor clock signal is being provided for execution of an application from the second clock generator. The second clock generator generates a clock at a lower speed than the first clock generator. After a predetermined time the first clock generator is reselected to provide the processor clock signal. The threshold detection is repeated until an optimum clock frequency is discovered.
    Type: Grant
    Filed: May 31, 2019
    Date of Patent: September 14, 2021
    Assignee: GRAPHCORE LIMITED
    Inventors: Stephen Felix, Mrudula Gore
  • Patent number: 11101736
    Abstract: A system may include a power supply configurable to generate any of a plurality of output voltages on a power supply output node. The system also may include a voltage auto-detection power distribution (PD) controller coupled to the power supply. The voltage auto-detection PD controller is configured to monitor an input signal for detection of presence of a device coupled to the system via a cable and assert combinations of a plurality of control signals. For each combination of control signals, the voltage auto-detection PD controller measures a value of an output voltage from the power supply, stores the measured value, and generates a plurality of packets for transmission to the device. Each packet contains a parameter indicative of a measured output voltage.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: August 24, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Deric Wayne Waters
  • Patent number: 11100230
    Abstract: In some embodiments, an apparatus can include a host board that has multiple connectors. Each connector from the multiple connectors removably connects to a unique compute device from multiple compute devices. The apparatus can further include a memory that stores a first firmware. The apparatus can further include a controller that is operatively coupled to the multiple connectors and the memory. The controller provides access to the first firmware by a compute device from the multiple compute devices when the compute device removably connects to the host board via a connector from the multiple connectors and when a circuit of the compute device disables access to the memory of the compute device to cause the compute device to continue a power-on cycle using the first firmware.
    Type: Grant
    Filed: July 6, 2020
    Date of Patent: August 24, 2021
    Assignee: Management Services Group, Inc.
    Inventor: Thomas S. Morgan
  • Patent number: 11068018
    Abstract: The invention concerns a computing system comprising: an island (102) comprising a group of circuits capable of operating in one of a plurality of operating modes, the island being coupled to an island control circuit (122); and a clock generation circuit (902) supplying a further clock signal to the island control circuit (122) for controlling a change of mode of the island, the clock generation circuit (902) being configured to select one of a plurality of clock frequencies for the further clock signal, the selection being based on the change of operating mode to be applied.
    Type: Grant
    Filed: April 8, 2019
    Date of Patent: July 20, 2021
    Assignee: Dolphin Design
    Inventors: Mathieu Louvat, Lionel Jure, Gauthier Reveret, Alexandre Charvier
  • Patent number: 11054873
    Abstract: A method and apparatus of a device that manages a thermal profile of a device by selectively throttling central processing unit operations of the device is described. The device manages a thermal profile of the device by adjusting a throttling a central processing unit execution of a historically high energy consuming task. In this embodiment, the device monitors thermal level of the thermal profile of the device, the device is executing a plurality of tasks that utilize a plurality of processing cores of the device. If the thermal level of the device exceeds a thermal threshold, the device identifies one of the plurality of tasks as a historically high energy consuming task, and throttles this historically high energy consuming task by setting a force idle execution time for the historically high energy consuming task. The device further executes the plurality of tasks.
    Type: Grant
    Filed: August 27, 2018
    Date of Patent: July 6, 2021
    Assignee: Apple Inc.
    Inventor: Derek R. Kumar
  • Patent number: 11048320
    Abstract: Computerized systems and methods are provided to intelligently and dynamically manage a data center comprising at least one server and at least one central manager. The central manager is programmed to access the at least one server on a predetermined schedule to determine whether at least one application is functioning properly by determining a functionality level. Alternatively, the central manager determines whether the at least one server is actively used by determining an activity level for the server. Based on the central manager's determinations, the system dynamically adjusts the power level of the server, resulting in reduced power consumption and a reduction in wasted resources and unnecessary processing power in the management of servers in a data center.
    Type: Grant
    Filed: December 27, 2017
    Date of Patent: June 29, 2021
    Assignee: CERNER INNOVATION, INC.
    Inventors: Karthikeyan Sukumaran, Sravan Kumar Anumula, Rakesh Reddy Yarragudi, Manipal Reddy Thoomukunta, Deepak Kumar Jain
  • Patent number: 11048540
    Abstract: Methods, apparatus, systems, and articles of manufacture to manage heat in a CPU are disclosed. An example apparatus includes a metric collection agent to output a metric representative of a property of the central processor unit including a first core and a second physical core, the first physical core and the second physical core mapped to first and second logical cores by a map. A policy processor is to evaluate the first metric to determine whether to change the map to remap at least one of the first and second logical cores relative to the second one of the first and the second physical cores to move a process between the first and second physical cores to adjust the property, the moving of the process between the physical cores being transparent to an application/OS layer. A mapping controller is responsive to the policy processor to change the map.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: June 29, 2021
    Assignee: Intel Corporation
    Inventors: Igor Duarte Cardoso, John OLoughlin, Louise Daly, Abdul Halim, Adrian Hoban
  • Patent number: 11048314
    Abstract: A system loading detecting device and method are provided. The system loading detecting device includes a processing device, a detection circuit and a controller. The detection circuit detects whether an adapter is unplugged from the system loading detecting device to generate a detection signal. When the adapter is unplugged from the system loading detecting device, the detection signal is changed from a first level to a second level. The controller is coupled to the detection circuit and the processing device. In addition, the controller receives the detection signal and determines whether to trigger the generation of a throttling signal according to the detection signal to enable a throttling mechanism to reduce system loading.
    Type: Grant
    Filed: May 13, 2019
    Date of Patent: June 29, 2021
    Assignee: QUANTA COMPUTER INC.
    Inventors: Ming-Tsung Ho, Chun-Jie Yu, Yu-An Huang
  • Patent number: 11042383
    Abstract: A system and method for boot speed optimization is discussed. Uncompressed copies of UEFI firmware volumes and OS boot loader files stored on a portion of an NVDIMM are used during a boot sequence in a computing platform. The cached copies on the NVDIMM are used during the boot sequence after a successful validation check is performed to provide faster boots of the computing platform.
    Type: Grant
    Filed: February 3, 2019
    Date of Patent: June 22, 2021
    Assignee: Insyde Software Corp.
    Inventors: Timothy Andrew Lewis, Trevor Western
  • Patent number: 11036274
    Abstract: An image processing apparatus includes a human sensor, an operation unit for performing various settings, and a control unit capable of switching an operation mode between a normal mode and a sleep mode. In a case where no inputting from the operation unit occurs in a first set time, the control unit switches from the normal mode to the sleep mode. In a case where a human body is detected by the human sensor, the control unit switches from the sleep mode to the normal mode. In the normal mode, when the human sensor no longer detects a human body or the human sensor detects a human body leaving, the control unit clears a setting of the operation unit and starts counting down a second set time set for switching from the normal mode to the sleep mode.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: June 15, 2021
    Assignee: SHARP KABUSHIKI KAISHA
    Inventor: Kazuyuki Ohnishi
  • Patent number: 11026176
    Abstract: Device wakeups can consume a significant amount of power with respect to the device's total power battery lifetime. Aspects of a method, apparatus, and computer-readable medium are presented herein that provide a solution to the problem of battery strain by improving the manner in which a wireless device coordinates device wakeup for multiple applications or multiple operations. An apparatus receives a wakeup time interval from each of a plurality of applications. The apparatus forms a first device wakeup time interval, the first device wakeup time interval including overlapping wakeup time intervals for the plurality of applications. The apparatus schedules a device wakeup during at least the first device wakeup time interval.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: June 1, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Hamza Ijaz Abbasi, Ralph Akram Gholmieh, Elmira Mazloomian, Liangchi Hsu, Alan Soloway, Osama Lotfallah, Carlos Marcelo Dias Pazos
  • Patent number: 11023029
    Abstract: In one embodiment, a method includes determining a plurality of hardware components of a system. The method also includes power cycling a first hardware component of the plurality of hardware components of the system according to a dynamic schedule. A period of time in which power cycling of the first hardware component takes place is shortened as the age of the first hardware component approaches the expected lifespan of the first hardware component. Also, the method includes determining whether the first hardware component experienced a power-up failure resulting from the power cycling. Moreover, the method includes outputting an indication to replace and/or repair the first hardware component in response to a determination that the first hardware component experienced the power-up failure resulting from the power cycling. Other systems, methods, ad computer program products for preventing unexpected power-up failures of individual hardware components are described in accordance with more embodiments.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Matthew G. Borlick, Brian J. Cagno, Lokesh M. Gupta, Karl A. Nielsen, Todd C. Sorenson
  • Patent number: 11023589
    Abstract: A multi-phase boot operation of a virtualization manager at a virtualization host is initiated at an offload card. In a first phase of the boot, a security key stored in a tamper-resistant location of the offload card is used. In a second phase, firmware programs are measured using a security module, and a first version of a virtualization coordinator is instantiated at the offload card. The first version of the virtualization coordinator obtains a different version of the virtualization coordinator and launches the different version at the offload card. Other components of the virtualization manager (such as various hypervisor components that do not run at the offload card) are launched by the different version of the virtualization controller.
    Type: Grant
    Filed: June 7, 2019
    Date of Patent: June 1, 2021
    Assignee: Amazon Technologies, Inc.
    Inventors: Anthony Nicholas Liguori, Barak Wasserstrom
  • Patent number: 11010475
    Abstract: According to certain general aspects, the present embodiments relate to providing a secure computer architecture in which a single computer is capable of simultaneously executing two operating systems. According to certain additional aspects, the two operating systems can have different security profiles and capabilities. According to still further aspects, the secure computer architecture further provides secure video conferencing capabilities, network activity monitoring and high performance computer graphics.
    Type: Grant
    Filed: October 6, 2017
    Date of Patent: May 18, 2021
    Assignee: Janus Technologies Inc.
    Inventor: Sofin Raskin
  • Patent number: 11003235
    Abstract: The invention introduces a non-transitory computer program product for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: May 11, 2021
    Assignee: SILICON MOTION, INC.
    Inventors: Chang-Wei Shen, Te-Kai Wang, Pin-Hua Chen
  • Patent number: 10990301
    Abstract: A memory module may include a memory device and a power controller. The memory device may operate by being supplied with a first memory power supply voltage and a second memory power supply voltage. The power controller may receive a first power supply voltage and a second power supply voltage from a power source, and supply the first memory power supply voltage and the second memory power supply voltage by changing levels of the first power supply voltage and the second power supply voltage based on operation state information.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: April 27, 2021
    Assignee: SK hynix Inc.
    Inventor: Jung Hyun Kim
  • Patent number: 10983585
    Abstract: The present invention relates to platform power management.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: April 20, 2021
    Assignee: Intel Corporation
    Inventors: Ren Wang, Christian Maciocco, Sanjay Bakshi, Tsung-Yuan Charles Tai
  • Patent number: 10969819
    Abstract: The present invention relates to a security control comprising a first controller having a first clock generator for generating a first clock signal, a separate second controller having a second clock generator for generating a second clock signal, wherein the first clock signal is output to a first input of the first controller and to a first input of the second controller, and the second clock signal is output to a second input of the first controller and to a second input of the second controller. In addition, the present invention relates to a method for operating a security control.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: April 6, 2021
    Assignee: WAGO Verwaltungsgesellschaft mbH
    Inventors: Maxim Laschinsky, Christian Voss