Abstract: A method of power management includes steps of: in response to receiving from a server host a sleep command, an expander first outputting a predetermined register value to a processing unit in a normal state, and then switching to a power-saving state and outputting an interrupt signal to the processing unit; the processing unit determining whether both the predetermined register value and the interrupt signal are received; and when it is determined that both the predetermined register value and the interrupt signal have been received, the processing unit controlling a power supply to output standby electricity, making the expander and the processing unit operate based on the standby electricity.

Abstract: A device for generating a supply or bias voltage and a clock signal for a synchronous digital circuit is provided. The device includes an oscillator circuit comprising a propagation path representative of a critical path of the circuit and which varies with a supply or bias voltage to the oscillator, and outputting a periodic signal, the frequency whereof depends on the propagation path delay; a resistive element; a switched capacitor coupled to the output of the oscillator such that the switching frequency thereof corresponds to the frequency of the periodic signal or to a multiple or divisor of this frequency; and an amplifier circuit outputting, from an output coupled to a power supply input or bias input of the oscillator, a voltage, the amplitude whereof is representative of a difference between the resistance R and the equivalent resistance of the switched capacitor.

Abstract: Examples discussed herein relate to managing power allocation for devices, such as network devices, with processing chip. In some examples, based on determining that a first temperature measurement of the processing chip does not satisfy an operating temperature threshold, the network device allocates power from a power source to a first heating element of the network device to heat the processing chip & allocates power from the power source to a second heating element of the network device to heat the processing chip. Based on determining that a second temperature measurement satisfies the operating temperature threshold, the network device allocates power from the power source to a set of power over ethernet ports of the network device & the first amount of power from the power source selectively to the first heating element to heat the processing chip.

Abstract: The present disclosure relates to a chip booting control method, a chip, a display panel, and an electronic apparatus. The method is applied to a control circuit of a chip, and the chip further includes a buffer. The method includes: reading first booting information from the buffer in response to a chip triggering non-power-down reset, the first booting information being used to boot the chip; determining whether the first booting information satisfies a first preset condition; and booting the chip according to the first booting information in response to the first booting information satisfying the first preset condition.

Abstract: The present technology proposes techniques for generating globally coherent timestamps. This technology may allow distributed systems to causally order transactions without incurring various types of communication delays inherent in explicit synchronization. By globally deploying a number of time masters that are based on various types of time references, the time masters may serve as primary time references. Through an interactive interface, the techniques may track, calculate and record data relative to each time master thus providing the distributed systems with causal timestamps.

Abstract: Techniques for dynamically configuring a device for a cloud-based environment and validating the configuration are described. One embodiment includes receiving a configuration request for a device and processing the configuration request to determine one or more customization characteristics. The device is configured with the one or more customization characteristics to dynamically update the device. A software module is selected from a repository for the device based on the one or more customization characteristics and installed on the device. Embodiments perform a multi-part verification operation on the device, where the multi-part verification operation includes at least a multi-cloud verification operation and a runtime behavior analysis.

Abstract: A computing-in-memory apparatus is provided, which includes a voltage regulator having an amplifier and a reference current source, a computing-in-memory array having a plurality of computing units and a detection circuit connected to each other. The amplifier has a current input and a voltage output and is connected to the reference current source, and the voltage regulator provides an output voltage for supplying to the computing-in-memory array. An output current of the detection circuit is inputted into the voltage regulator to compare with the reference current source of the voltage regulator, and then a negative feedback convergence or a negative feedback mechanism is executed according to the comparison result to regulate the output voltage supplied by the voltage regulator to the computing-in-memory array.

Abstract: A power adapter provides power to an information handling system. The power adapter includes a power supply and a power delivery controller. The power supply receives an alternating current (AC) input at one of a plurality of input voltages, and provides a direct current (DC) output at one of a plurality of output voltages, each output voltage being associated with a current limit.

Abstract: A line module for use in a network device a plurality of circuits; and a power module comprising at least one circuit, wherein the power module is connected to the plurality of circuits and a Power Distribution Unit (PDU), and the at least one circuit of the power module is configured to shut down one or more of the plurality of circuits until a current threshold is no longer exceeded by a current drawn from a power feed connected to the first PDU.

Abstract: A basic input output system (BIOS) of an information handling system may access a first list indicating one or more activation statuses of one or more BIOS firmware modules. The BIOS may determine a BIOS firmware module of the one or more BIOS firmware modules to load based, at least in part, on the first list. The BIOS may load the determined BIOS firmware module during booting of the information handling system.

Abstract: Apparatuses, methods and storage medium for providing access from outside a multicore processor System on Chip (SoC) are disclosed herein. In embodiments, an SoC may include a memory to store a plurality of embedded values correspondingly associated with a plurality of architecturally identical cores. Each embedded value may indicate a default voltage for a respective one of the plurality of architecturally identical cores. In embodiments, an apparatus may include one or more processors, devices, and/or circuitry to provide access from outside the multicore processor SoC to individually configure voltages of the plurality of architecturally identical cores to values that are different than the values of the default voltages. Other embodiments may be described and/or claimed.

Abstract: A system includes an electronic module and an integrated circuit outside the electronic module. The integrated circuit is configured to generate a digital timing signal that emulates a first synchronization signal internal to the module and not available outside the module and to generate trigger signals based on the digital timing signal. A controller is configured to independently and autonomously perform control operations of the electronic module at times triggered by the trigger signals.

Abstract: A server power-down detection method and system, a device, and a storage medium are disclosed, wherein the method includes: in response to the completion of hardware power on, controlling a PCH to read BIOS codes from BIOS flash storage particles via a first interface and running the BIOS codes; detecting whether bits of a register of the PCH have been set; in response to the bits of the register of the PCH being set, controlling the PCH to send power-down completion information to a BMC via a second interface; and in response to the BMC receiving the power-down completion information, recording the power-down completion information in BMC flash storage particles, and performing the hardware power on again until a test is completed.

Abstract: The present invention discloses a power supply apparatus having power limiting mechanism. A switch transistor is controlled by a control voltage such that a power supply unit supplies a power to a powered device when the switch transistor is controlled to be conducted, wherein the switch transistor has an operation current, an operation voltage and an operation power under conduction. A voltage detection circuit detects the operation voltage. A power-limiting circuit performs analog-to-digital conversion on the operation voltage, generates a current-limiting signal related to a current-limiting value according to the operation voltage based on a predetermined voltage-current curve and performs digital-to-analog conversion on the current-limiting signal to generate a reference voltage.

Abstract: A semiconductor device includes a clock terminal to and from which a clock is allowed to be input and output, and a data terminal to and from which data is allowed to be input and output. In the semiconductor device, the data synchronized with the clock that is input to the clock terminal or is output from the clock terminal is output from the data terminal, and when the clock is output from the clock terminal, the clock is output irrespective of whether or not data transfer of the data is being executed.

Abstract: An information recording apparatus has a drive unit to record digital information including digital contents; and a host unit to control reading and writing of the digital information for the drive unit. The host unit has a network processing unit to communicate with a server, a shadow determination unit to determine whether a shadow boot program to be executed prior to a boot program is executable, a shadow reading unit to read the shadow program from the drive unit when the shadow determination unit determines to be executable, a shadow execution unit to execute the shadow program, a server authentication unit to perform authentication with the server in accordance with a processing of the shadow program, and a password transmitter to transmit to the drive unit a password used for unlock of the drive unit when the authentication with the server is successful.

Abstract: A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.

Abstract: Methods and systems are disclosed that initiate, during a power-on self-test of a computer system, a pre-registered handler for accessing, modifying, or a combination thereof one or more registers within a basic input output system (BIOS) of the computer system. A request to access, modify, or a combination thereof at least one register of the one or more registers within the BIOS is received during runtime of an operating system of the computer system. The request with the pre-registered handler is processed to access, modify, or a combination thereof at least one register of the one or more registers within the BIOS corresponding to the request. A response to the request is provided based on data from the at least one register obtained by the pre-registered handler.

Abstract: Aspects of the disclosure include a non-transitory computer-readable medium storing computer-executable instructions for controlling at least one uninterruptible power supply (UPS) configured to provide power to at least one server executing one or more services, the instructions instructing at least one processor to receive an indication of the services initiating a shutdown procedure, determine that a predicted shutdown time (PST) of the shutdown procedure exceeds a baseline shutdown time (BST) to perform the shutdown procedure, the BST being less than an available runtime of the UPS, control the UPS to continue providing power to the server responsive to determining that the PST is less than the available runtime and that the PST exceeds the BST, receive an indication that the shutdown procedure is successfully executed over an actual shutdown time (AST), and update the BST responsive to determining that the AST is different than the BST.

Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.