Abstract: Methods and systems are disclosed that initiate, during a power-on self-test of a computer system, a pre-registered handler for accessing, modifying, or a combination thereof one or more registers within a basic input output system (BIOS) of the computer system. A request to access, modify, or a combination thereof at least one register of the one or more registers within the BIOS is received during runtime of an operating system of the computer system. The request with the pre-registered handler is processed to access, modify, or a combination thereof at least one register of the one or more registers within the BIOS corresponding to the request. A response to the request is provided based on data from the at least one register obtained by the pre-registered handler.

Abstract: A memory system includes a memory chip and a memory controller that controls the memory chip. In a write operation, the memory controller transfers a first timing signal synchronized with a first clock and first data synchronized with the first timing signal to the memory chip. In a read operation, the memory controller transfers a second timing signal synchronized with at least a second clock to the memory chip. The second clock has a frequency different from a frequency of the first clock. In the read operation, the memory chip generates a third timing signal synchronized with the second clock based on the second timing signal, and transfers the third timing signal and second data synchronized with the third timing signal to the memory controller.

Abstract: Aspects of the disclosure include a non-transitory computer-readable medium storing computer-executable instructions for controlling at least one uninterruptible power supply (UPS) configured to provide power to at least one server executing one or more services, the instructions instructing at least one processor to receive an indication of the services initiating a shutdown procedure, determine that a predicted shutdown time (PST) of the shutdown procedure exceeds a baseline shutdown time (BST) to perform the shutdown procedure, the BST being less than an available runtime of the UPS, control the UPS to continue providing power to the server responsive to determining that the PST is less than the available runtime and that the PST exceeds the BST, receive an indication that the shutdown procedure is successfully executed over an actual shutdown time (AST), and update the BST responsive to determining that the AST is different than the BST.

Abstract: In an embodiment, a processor includes a core domain with a plurality of cores and a power controller having a first logic to receive a first request to increase an operating voltage of a first core of the core domain to a second voltage, to instruct a voltage regulator to increase the operating voltage to an interim voltage, and to thereafter instruct the voltage regulator to increase the operating voltage to the second voltage. Other embodiments are described and claimed.

Abstract: Embodiments of systems and methods for power throttling of High Performance Computing (HPC) components are described. In some embodiments, an HPC platform may include: a system Baseboard Management Controller (BMC), and an accelerator tray comprising a tray BMC coupled to a plurality of managed subsystems and to the system BMC, where the system BMC is configured to: in response to a power excursion event, instruct the tray BMC to throttle a first managed subsystem by a first amount and to throttle a second managed subsystem by a second amount.

Abstract: Respective energy consumption data is collected via respective agents running on respective host servers. The respective energy consumption data represents energy consumed by the respective host servers over a time period. The respective agents communicate with hardware on each of the respective host servers using a unified application programming interface (API). Respective energy costs are determined over the time period for the respective host servers based on the respective energy consumption data. A subset of the respective host servers that are being underutilized is identified based on the respective energy consumption data and the respective energy costs. An action to take with respect to the subset of the respective host servers that are being underutilized is determined to reduce the energy costs.

Abstract: An electronic device is provided. The electronic device includes a power pin, a main circuit, and a start-up circuit. The power pin is configured to receive a power supply. The start-up circuit includes a switch coupled between the power pin and the main circuit, a timer and an oscillator. The switch is configured to selectively provide the power supply to the main circuit in response to a control signal. The oscillator, is configured to provide a periodic signal. The timer is configured to provide the control signal to turn on the switch when counting to a start-up time according to the periodic signal, so that the main circuit is configured to provide a fixed voltage according to the power supply.

Abstract: Eyewear including a support structure defining a region for receiving a head of a user. The support structure supports optical elements, electronic components, and a use detector. The use detector is coupled to the electronic components and is positioned to identify when the head of the user is within the region defined by the support structure. The electronic components monitor the use detector and transition from a first mode of operation to a second mode of operation when the use detector senses the head of the user in the region.

Abstract: A method is provided for authenticating firmware images in an embedded system. The method may include loading and executing a trusted firmware using a pre-existing Secure Boot on a baseboard management controller (BMC). The BMC is configured as a master for an embedded system including System On Chips (SOCs) configured as slaves, out-of-band interfaces between the BMC and the SOCs, and flash storages in electrical communication with the SOCs. The method may also include pushing or uploading, by the BMC, a secure SOC firmware image to one of the SOCs using one of the out-of-band interfaces, verifying a digital signature extracted from the SOC firmware image by using a hash code calculated from the SOC firmware image and decrypted using a public key stored on the BMC and notifying a user about verification of the digital signature.

Abstract: A computing system is provided. The computing system includes a central processing unit (CPU), a baseboard management controller (BMC), and a boot non-volatile memory. The BMC selects a boot partition in the computing system. The boot non-volatile memory stores at least two boot partitions as a primary boot area including a basic input/output system (BIOS) image and a secondary boot area including a BMC image. The BMC switches between the secondary boot area to boot the BMC and the primary boot area to boot the BIOS. Only one of the primary boot area or the secondary boot area is accessible when the BIOS is booting or when the BMC is booting.

Abstract: Techniques in electronic systems, such as in systems including a processing chip and one or more external memory chips, provide improvements in one or more of system security (such as intrusion and/or virus/malware prevention), performance, cost, and efficiency. For example, the processing chip includes at least one CPU and circuitry enabling the at least one CPU to securely boot from an external, non-volatile memory chip containing encrypted, executable code. The circuitry comprises immutable hardware to copy the executable code from the non-volatile memory to another external memory from which the at least one CPU is able to access it. The encryption uses a key created at a manufacturing time of and unique to the processing chip that is never CPU-accessible, forming a secure hardware association between the processing chip and the non-volatile memory chip.

Abstract: A networked system includes a computing device having a central processing system and accelerator system(s). A central processor/accelerator power management system coupled to the computing device via a network operates to deploy workload(s) on the computing device and receive workload performance information from the computing device that identifies a central processing system utilization of the central processing system in performing the workload(s) and an accelerator system utilization of each accelerator system in performing the workload(s). Based on the workload performance information, the computing device determines a first power consumption ratio of the central processing system and the accelerator system(s) in performing the workload(s), and modifies operation of at least one of the central processing system and the accelerator system(s) to change the first power consumption ratio to a second power consumption ratio that is more power efficient than the first power consumption ratio.

Abstract: Disclosed herein are embodiments related to security in cloudlet environments. In some embodiments, for example, a computing device (e.g., a cloudlet) may include: a trusted execution environment; a Basic Input/Output System (BIOS) to request a Key Encryption Key (KEK) from the trusted execution environment; and a Self-Encrypting Storage (SES) associated with the KEK; wherein the trusted execution environment is to verify the BIOS and provide the KEK to the BIOS subsequent to verification of the BIOS, and the BIOS is to provide the KEK to the SES to unlock the SES for access by the trusted execution environment.

Abstract: A system to facilitate operating system (OS) installation is described. The system includes a server and rack controller, including one or more processors to generate an imaging service comprising an OS image container, transmit data via a first network to initiate a boot up process at a server and download an OS image included in the OS image container via a second network, wherein the second network is separate from the first network.

Abstract: The present invention relates to platform power management.

Abstract: A method of regulating usage of an electronic device is provided that includes at least one remote server, a user personal computing (PC) device, an administrator PC device, at least one electronic device, and a computerized regulating adapter. The method begins by monitoring a current date-and-time with the computerized regulating adapter. An electrical plug is then physically secured to the computerized regulating adapter with a locking mechanism of the computerized regulating adapter. The electronic device is then electrically powered with the computerized regulating adapter, if the current date-and-time is any date-and-time from the plurality of available date-and-times. The electronic device is then disabled with the computerized regulating adapter, if the current date-and-time matches an arbitrary blocked date-and-time, wherein the arbitrary blocked date-and-time is any date-and-time from the plurality of blocked date-and-times.

Abstract: The invention introduces a non-transitory computer-readable storage medium for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

Abstract: A power supply control unit controls supply and stoppage of power to a plurality of blocks having two or more modules. A clock control unit controls supply and stoppage of clocks to the two or more modules in the plurality of blocks. A first control unit verifies validity of a program stored in a storage unit. A second control unit executes the program determined to be valid as a result of verification by the first control unit. While the program is verified by the first control unit, the power supply control unit supplies power to a block including a module required for the verification, and the clock control unit stops a clock to a module not required for the verification of the block including a module required for the verification.

Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level supply voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.