Abstract: An electronic device is provided. The electronic device includes a power pin, a main circuit, and a start-up circuit. The power pin is configured to receive a power supply. The start-up circuit includes a switch coupled between the power pin and the main circuit, a timer and an oscillator. The switch is configured to selectively provide the power supply to the main circuit in response to a control signal. The oscillator, is configured to provide a periodic signal. The timer is configured to provide the control signal to turn on the switch when counting to a start-up time according to the periodic signal, so that the main circuit is configured to provide a fixed voltage according to the power supply.

Abstract: Eyewear including a support structure defining a region for receiving a head of a user. The support structure supports optical elements, electronic components, and a use detector. The use detector is coupled to the electronic components and is positioned to identify when the head of the user is within the region defined by the support structure. The electronic components monitor the use detector and transition from a first mode of operation to a second mode of operation when the use detector senses the head of the user in the region.

Abstract: A method is provided for authenticating firmware images in an embedded system. The method may include loading and executing a trusted firmware using a pre-existing Secure Boot on a baseboard management controller (BMC). The BMC is configured as a master for an embedded system including System On Chips (SOCs) configured as slaves, out-of-band interfaces between the BMC and the SOCs, and flash storages in electrical communication with the SOCs. The method may also include pushing or uploading, by the BMC, a secure SOC firmware image to one of the SOCs using one of the out-of-band interfaces, verifying a digital signature extracted from the SOC firmware image by using a hash code calculated from the SOC firmware image and decrypted using a public key stored on the BMC and notifying a user about verification of the digital signature.

Abstract: A computing system is provided. The computing system includes a central processing unit (CPU), a baseboard management controller (BMC), and a boot non-volatile memory. The BMC selects a boot partition in the computing system. The boot non-volatile memory stores at least two boot partitions as a primary boot area including a basic input/output system (BIOS) image and a secondary boot area including a BMC image. The BMC switches between the secondary boot area to boot the BMC and the primary boot area to boot the BIOS. Only one of the primary boot area or the secondary boot area is accessible when the BIOS is booting or when the BMC is booting.

Abstract: Techniques in electronic systems, such as in systems including a processing chip and one or more external memory chips, provide improvements in one or more of system security (such as intrusion and/or virus/malware prevention), performance, cost, and efficiency. For example, the processing chip includes at least one CPU and circuitry enabling the at least one CPU to securely boot from an external, non-volatile memory chip containing encrypted, executable code. The circuitry comprises immutable hardware to copy the executable code from the non-volatile memory to another external memory from which the at least one CPU is able to access it. The encryption uses a key created at a manufacturing time of and unique to the processing chip that is never CPU-accessible, forming a secure hardware association between the processing chip and the non-volatile memory chip.

Abstract: A networked system includes a computing device having a central processing system and accelerator system(s). A central processor/accelerator power management system coupled to the computing device via a network operates to deploy workload(s) on the computing device and receive workload performance information from the computing device that identifies a central processing system utilization of the central processing system in performing the workload(s) and an accelerator system utilization of each accelerator system in performing the workload(s). Based on the workload performance information, the computing device determines a first power consumption ratio of the central processing system and the accelerator system(s) in performing the workload(s), and modifies operation of at least one of the central processing system and the accelerator system(s) to change the first power consumption ratio to a second power consumption ratio that is more power efficient than the first power consumption ratio.

Abstract: Disclosed herein are embodiments related to security in cloudlet environments. In some embodiments, for example, a computing device (e.g., a cloudlet) may include: a trusted execution environment; a Basic Input/Output System (BIOS) to request a Key Encryption Key (KEK) from the trusted execution environment; and a Self-Encrypting Storage (SES) associated with the KEK; wherein the trusted execution environment is to verify the BIOS and provide the KEK to the BIOS subsequent to verification of the BIOS, and the BIOS is to provide the KEK to the SES to unlock the SES for access by the trusted execution environment.

Abstract: A system to facilitate operating system (OS) installation is described. The system includes a server and rack controller, including one or more processors to generate an imaging service comprising an OS image container, transmit data via a first network to initiate a boot up process at a server and download an OS image included in the OS image container via a second network, wherein the second network is separate from the first network.

Abstract: The present invention relates to platform power management.

Abstract: A method of regulating usage of an electronic device is provided that includes at least one remote server, a user personal computing (PC) device, an administrator PC device, at least one electronic device, and a computerized regulating adapter. The method begins by monitoring a current date-and-time with the computerized regulating adapter. An electrical plug is then physically secured to the computerized regulating adapter with a locking mechanism of the computerized regulating adapter. The electronic device is then electrically powered with the computerized regulating adapter, if the current date-and-time is any date-and-time from the plurality of available date-and-times. The electronic device is then disabled with the computerized regulating adapter, if the current date-and-time matches an arbitrary blocked date-and-time, wherein the arbitrary blocked date-and-time is any date-and-time from the plurality of blocked date-and-times.

Abstract: The invention introduces a non-transitory computer-readable storage medium for adjusting operating frequencies when executed by a processing unit of a device, containing program code to: collect an interface-activity parameter comprising information about data transmissions on a host access interface and/or a flash access interface; select one from multiple frequencies according to the interface-activity parameter; and drive a clock generator to output a clock signal at the selected frequency, thereby enabling the host access interface and/or the flash access interface to operate at an operating frequency.

Abstract: In some embodiments, clock input buffer circuitry and divider circuitry use a combination of externally-suppled voltages and internally-generated voltages to provide the various clock signals used by a semiconductor device. For example, a clock input buffer is configured to provide second complementary clock signals responsive to received first complementary clock signals using cross-coupled buffer circuitry coupled to a supply voltage and to drive the first complementary clock signals using driver circuitry coupled to an internal voltage. In another example, a divider circuitry may provide divided clock signals based on the second complementary clock signals via a divider coupled to the internal voltage and to drive the divided clock signals using driver circuitry coupled to the supply voltage. A magnitude of the supply voltage may be less than a magnitude of the internal voltage.

Abstract: A hierarchical, scalable power delivery system is disclosed. The power delivery system includes a first level of power converter circuitry configured to generate one or more first level regulated supply voltages, and a second level of power converter circuitry configured to generate one or more second level regulated supply voltages. The first level of power converter circuitry receives an input supply voltage, while the second level power converter circuitry receives the one or more first level supply voltages. The second level power converter circuitry is configured to provide the second level regulated supply voltages to a computing element configured to operate as a single, logical computer system, the computing element being configured to operate in a number of power configurations having differing numbers of load circuits. Different portions of the hierarchical power delivery system may be selectively enabled for corresponding ones of the power configurations of the computing element.

Abstract: A power supply control unit controls supply and stoppage of power to a plurality of blocks having two or more modules. A clock control unit controls supply and stoppage of clocks to the two or more modules in the plurality of blocks. A first control unit verifies validity of a program stored in a storage unit. A second control unit executes the program determined to be valid as a result of verification by the first control unit. While the program is verified by the first control unit, the power supply control unit supplies power to a block including a module required for the verification, and the clock control unit stops a clock to a module not required for the verification of the block including a module required for the verification.

Abstract: A semiconductor integrated circuit includes a first circuit connected to a power supply line, a determination portion configured to determine whether a voltage drop in the power supply line affects an operation of the first circuit, and a power supply voltage control portion configured to control change of a power supply voltage value on the basis of a determination result of the determination portion.

Abstract: A method of controlling a memory device can include: determining, by the memory device, a time duration in which the memory device is in a standby mode; automatically switching the memory device from the standby mode to a power down mode in response to the time duration exceeding a predetermined duration; exiting from the power down mode in response to signaling from a host device via an interface; and toggling a data strobe when data is ready to be output from the memory device in response to a read command from the host device.

Abstract: A Computational Digital Low Dropout (CDLDO) regulator is described that computes a required solution for regulating an output supply as opposed to traditional feedback controllers. The CDLDO regulator is Moore's Law friendly in that it can scale with technology nodes. For example, CDLDO regulator of some embodiments uses a digital approach to voltage regulation, which is orders of magnitude faster than traditional digital LDOs and enables regulation at GHz speeds, making fast dynamic DVFS a reality. The CDLDO also autonomously tunes out the effects of process-voltage-temperature (PVT) and other non-idealities making the settling time totally variation tolerant.

Abstract: In some embodiments, an apparatus can include a host board that has multiple connectors. Each connector from the multiple connectors removably connects to a unique compute device from multiple compute devices. The apparatus can further include a memory that stores a first firmware. The apparatus can further include a controller that is operatively coupled to the multiple connectors and the memory. The controller provides access to the first firmware by a compute device from the multiple compute devices when the compute device removably connects to the host board via a connector from the multiple connectors and when a circuit of the compute device disables access to the memory of the compute device to cause the compute device to continue a power-on cycle using the first firmware.

Abstract: Computerized systems and methods are provided to intelligently and dynamically manage a data center comprising at least one server and at least one central manager. The central manager is programmed to access the at least one server on a predetermined schedule to determine whether at least one application is functioning properly by determining a functionality level. Alternatively, the central manager determines whether the at least one server is actively used by determining an activity level for the server. Based on the central manager's determinations, the system dynamically adjusts the power level of the server, resulting in reduced power consumption and a reduction in wasted resources and unnecessary processing power in the management of servers in a data center.

Abstract: An information handling system may include a processor and a basic input/output system (BIOS) comprising a program of instructions comprising boot firmware configured to be the first code executed by the processor when the information handling system is booted or powered on, the BIOS configured to, during boot of the information handling system: (i) read a predefined measurement of an order of loading of BIOS drivers configured to execute during execution of the BIOS, such predefined measurement made during build of the BIOS; (ii) perform a runtime measurement of an order of loading of the BIOS drivers during actual runtime of the information handling system; (iii) compare the predefined measurement to the runtime measurement; and (iv) responsive to a mismatch between the predefined measurement and the runtime measurement, respond with a remedial action.