Abstract: A computer chip including a data transfer network which comprises a plurality of communications links for transmitting data, a plurality of communication nodes, and a plurality of modules. Each of the communication nodes is directly connected to two or more other communication nodes through respective ones of the communications links. Each communication node is operable to communicate data over the respective one of the communications links. Each module is coupled to at least one of the communication nodes, and the modules are operable to communicate with each other through the communication nodes. The communication nodes are operable to create dynamic routes for the data transferred between any two or more of the plurality of modules over the respective ones of the communications links. The communication nodes form the dynamic routes controlled by a network configuration manager.

Abstract: A method and apparatus for detecting a predischarge node in an integrated circuit. The apparatus comprises a computer capable of being configured to execute a rules checker program which analyzes information relating to the integrated circuit to determine whether a predischarge node exists in the integrated circuit. The rules checker program evaluates each node in the integrated circuit and determines whether or not an N field effect transistor (NFET) is connected to the node and, if so, whether the gate terminal of the NFET is connected to a clock and whether a drain or source terminal of the NFET is connected to ground. The rules checker program also determines whether or not a P field effect transistor (PFET) is connected to the node being evaluated and, if so, whether it has a gate terminal which is not connected to a clock and drain and source terminals which are not connected to a supply.

Abstract: A method for routing conductive paths between a first datapaths and a second datapath in an integrated circuit is described. The method includes determining the degree of alignment between block one from the first datapath to block one from the second datapath, and determining the degree of alignment between block N from the first datapath to block N from the second datapath; Following the determination of the degree of alignment, the least aligned block pair to be routed is chosen from block one and block N. Next, a first horizontal track location to be used for routing the desired connection between said first datapath and said second datapath is chosen, and the corresponding conductive path is then routed using that track location. For each of the remaining unrouted block pairs, the next block pair to be routed is chosen to be the block pair immediately adjacent to the most recently routed block pair.

Abstract: The method and system for aiding in the design of an automotive vehicle enables dynamic placement of particle injection points into a flow domain to permit visual observation and alteration of resulting particle trajectories with respect to a computer aided design model representative of the vehicle. Various particle trajectories, representing windshield washer spray, water droplets along the vehicle surface, and the like can be simulated relative to the vehicle surface with or without the influence of a flow field around the vehicle surface to evaluate a vehicle design, compare alternate designs and compare results from physical aerodynamic tests to predicted results.

Abstract: A system and method for designing an integrated circuit device by selectively reducing power lines based on wiring demand of the device are provided. In one embodiment, a power demand value of a region of the device is determined and a wiring demand value of the region of the device is determined. Based on the wiring demand value and the power demand Value, power lines in the region are selectively reduced. These steps may be repeated for each region of the device and a new power line layout may be generated after stepping through each of the regions. The reduction of power lines may be repeated until an acceptable power line layout is produced. Based on this layout, detailed signal wiring can be performed. This technique can, for example, more efficiently allocate power lines and signal wires and increase the density of the integrated circuit chip.

Abstract: The step size parameters of a component placement machine are represented as genes in a component placement chromosome, and evolutionary algorithm techniques are applied to evolve offspring that have step size parameters that provide an improved component placement throughput estimate. The offspring that have these preferential step size parameters are used to generate additional offspring that provide further improvement in the component placement throughput estimate. After a number of generations, the step size parameters of the offspring that provides the best component placement throughput are used to program the component placement machine to achieve this improved throughput.

Abstract: A demultiplexer for a two-dimensional array of a plurality of nanometer-scale switches (molecular wire crossbar network) is disclosed. Each switch comprises a pair of crossed wires which form a junction where one wire crosses another and at least one connector species connecting said pair of crossed wires in said junction. The connector species comprises a bi-stable molecule. The demultiplexer comprises a plurality of address lines accessed by a first set of wires in the two-dimensional array by randomly forming contacts between each wire in the first set of wires to at least one of the address lines. The first set of wires crosses a second set of wires to form the junctions. The demultiplexer solves both the problems of data input and output to a molecular electronic system and also bridges the size gap between CMOS and molecules with an architecture that can scale up to extraordinarily large numbers of molecular devices.

Abstract: A system and method for detecting a type of a short of a plurality of types of shorts in a circuit in a semiconductor device is disclosed. The circuit includes a plurality of power supply lines and a plurality of ground lines. The short is between at least one of the plurality of power supply lines and at least one of the plurality of ground lines. In one aspect, the method and system include providing a library including a plurality of sets of current-voltage characteristics. Each of the plurality of sets of current-voltage characteristics is for a particular type of short of the plurality of types of shorts. In this aspect, the method and system further include measuring a particular set of current-voltage characteristics of the semiconductor device and comparing the particular set of current-voltage characteristics to the plurality of sets of current-voltage characteristics in the library.

Abstract: Exceptions allow a circuit designer, working with a circuit synthesis system, to specify certain paths through the circuit to be synthesized as being subject to non-default timing constraints. The additional information provided by the exceptions can allow the synthesis system to produce a more optimal circuit. A tag-based timing analysis tool is presented, which implements exceptions, and can be used in a synthesis system. A circuit is analyzed in “sections,” which comprise a set of “launch” flip flops, non-cyclic combinational circuitry and a set of “capture” flip flops. The tag-based static timing analysis of the present invention is performed in four main steps: preprocessing, pin-labeling, RF timing table propagation and relative constraint analysis. Preprocessing converts the exceptions written by the circuit designer into a certain standard form in which paths through the circuit to be synthesized are expressed in terms of circuit “pins.

Abstract: One embodiment of the present invention provides a system that creates a layout of a circuit by placing gates at specific locations in a circuit design based upon drive strengths and wireloads of gates in the circuit. The system operates on a gate-level description of the circuit, which includes a specification of gates in the circuit and a specification of a set of interconnections between the gates. From this gate-level description, the system obtains drive strength information for specific gates in the circuit, and uses this drive strength information as a factor in optimizing a placement for the gates in order to meet a set of timing constraints. The system may also use wireload information—in addition to the drive strength information—to place the gates. A variation on the above embodiment subsequently performs a timing-based placement operation to further optimize the drive strength-based placement. Another variation associates weights with drive strengths for individual gates.

Abstract: A method and system for programming the hardware of field programmable gate arrays and related reconfigurable resources as if they were software by creating hardware objects that implement application level functionalities, operating system functionalities, and hardware functionalities. Further controlling and executing the hardware objects via high level software constructs and managing the reconfigurable resources, such that the reconfigurable resources are optimized for the tasks currently executing.

Abstract: An input/output bus architecture that includes: an input/output bus; an input/output device connected to the input/output bus; a main processor, connected to the input/output bus, for executing a device driver corresponding to the input/output device, the device driver generating load/store commands for the input/output device; and a load/store assist engine, connected to the input/output bus and yet independent of the main processor, for loading/storing data to/from the input/output device according to the load/store commands from the device driver. The load/store assist engine decouples the main processor from latencies associated with execution of the load/store commands. The device driver is reassigned to the main processor, rather than being found in a device that is external to the main processor, such as an input/output processor.

Abstract: A system and method for increasing the flexibility of communications being performed by an integrated circuit Specifically, an integrated circuit including a programmable input/output processor and an attendant method of use thereof are disclosed. The integrated circuit comprises a main functional unit operable to perform a computing function and to fulfill an input/output (I/O) request, a memory coupled to the main functional unit, a programmable logic coupled to the main functional unit; and a plurality of I/O pads coupled to the programmable logic. The memory is operable to store one or more of a plurality of configurations for the programmable logic. The main functional unit is further operable to read the one or more of the plurality of configurations stored in the memory. The main functional unit is also operable to configure the programmable logic with a desired configuration from the plurality of configurations.

Abstract: A method and system for converting an architecture-specific design of a first type into an architecture-specific design of a second type such that race conditions and other anomalies are detected in the second type. By identifying routing delays in a first architecture and what those same routing delays would be in a second architecture, the method and system verify that a design has been properly converted. The method and system are applicable to the conversion of programmable interconnect logic devices to mask programmable logic devices. For example, a method for verifying timing for a design implemented in a new device when the design is to be moved from an old device. The method is particularly useful for verifying timing in a mask programmable device (HardWire) when the design is being converted from a field programmable device (FPGA).

Abstract: The layout of a semiconductor IC is determined making use of a first logical cell of an ordinary flip-flop based on a logical net. Logical simulation is performed according to the result of the layout, that is, the layout information. The possibility of erroneous operation caused by timing deviations is verified by comparing the timing information from the result of the logical simulation with the design specifications. Furthermore, the logical cells at points where there is the possibility of erroneous operation caused by timing deviations are replaced by second or third logical cells having delay elements connected to data input or output terminals of the flip-flops. The final layout of the semiconductor IC is then decided.

Abstract: A system for designing integrated circuits that use frequency synthesizers to ensure testability. A testability circuit is added or connected to the frequency synthesizer that will receive allow the integrated circuit to operate in a system mode for normal function and in a test mode during testing. In the test mode, the testability circuit will inhibit the reset signal from initializing the integrated circuit until the frequency synthesizer has reached phase lock. The testability circuit may be implemented as a component in the frequency synthesizer cell in an ASIC design system such that anytime the frequency synthesizer is used, the integrated circuit is testable.

Abstract: A field-programmable gate array device (FPGA) having plural rows and columns of logic function units is organized with symmetrical and complementary Variable Grain Architecture (VGA) and Variable Length Interconnect Architecture (VLI). Synthesis mapping exploits the diversified and symmetric resources of the VGA and VLI to efficiently pack function development into logic units of matched granularity and to transfer signals between logic units with interconnect lines of minimal length.

Abstract: Testcases are run to test the design of an integrated circuit. The coverage of the testcases is evaluated and compared against one or more microarchitecture models that define the behavior of a portion of the integrated circuit. If the coverage of the testcases is not adequate, new testcases are generated to test the previously untested behavior specified in the microarchitecture models.

Abstract: The present invention is a method and apparatus of routing a 1 of N signal to reduce the effective signal coupling between the signal wires. The present invention is a wire pack with a plurality of wires for routing a 1 of N signal in a semiconductor device. While routing the wires of the wire pack, the present invention rotates the route of each individual wire to reduce the signal coupling between the wires. Additionally, an isolation barrier borders the outside of the wire pack to further reduce the signal coupling. The rotation of the wires allow each individual wire be adjacent to each other wire for part of the wire's route. Other embodiments of the present invention include routing 1 of 3 signals and 1 of 4 signals.

Abstract: A method for designing a circuit on a spherical shaped semiconductor device using a great circle and a small, which is either parallel or perpendicular to the great circle, to define critical dimensions needed for the circuit. A great-circle-small-circle framework is used that has at least one great circle and one small circle that define a critical dimension on the surface of the sphere.